assembly also includes qualifier selection for conditionaI branching, input/output (I/O) port
decoding, and the main clock circuits.
Data Transfer Register @
U2, U7, U8, and U9 form a 16-bit Data Transfer Register which can be loaded or output onto
either the Instrument Bus (through U16 and U17, the Instrument Bus Drivers) or the Digital
Storage Bus (through U3, U4, and U5, the Digital Storage Bus Drivers).
Instrument Address Decoder @
U6, U14, and U15 control the loading and output of data between the Data Transfer Register
and the Instrument Bus.
Qualifier Select @
controlled by A3A6 Main Control firmware.
I/O Port Decoder @I
U18 and U19 decode I/O port control signals from the Pipeline Registers in A3A6 Main
Control.
Timing Generator @
Digital Storage.