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Control Logic @j
Control Logic generates control signals for display memory and buffers in Memory Data Input
Register. When control line CE (chip enable) is true, RAM address 11 @All) from U7
generates low chip enable 1 and 2 (LCEl, LCE2). Thi s enables the lower or upper block of
display memory during read and write operations.
During read operations, LOE (low output enable) is generated in U17D when CE is true
and LWRITE (low write) is false. During write operations, U17C produces LWE (low write
enable) when CE and LWRITE are true.
two inverters delay the rising edge of LDINEN to hold the data lines after LWE goes false, at
the end of a write operation.
Character Stroke Memory @
ROM U2 is a 2048 word by 8-bit read-only memory that contains the relative X and Y axis
coordinate information that forms displayed characters. Each 8-bit word contains three bits
of X-axis information, four bits of Y-axis information, and one bit for blanking. The ROM is
addressed from the memory address register and the stroke counter. The ROM outputs are
enabled by LROMEN (low ROM enable).
Stroke Counter @
The stroke counter drives the lower three address bits of character stroke memory. Since
most characters contain less than eight line segments, the character information is stored in
consecutive 8-word blocks in the ROM. The memory address register contains the address of
the 8-word block while the stroke counter contains the address of the individual strokes. To
read the information for all the line segments of a character, the memory address register is
held constant while the stroke counter addresses up to eight strokes.
The STROK8 output goes high to signal the processor that the eighth stroke has been
reached. LCLRSA clears the counter at the beginning of each character and INCRSA is used
to increment the counter after each stroke.
2
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