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It receives AX and AY signals from A3A3 Line Generator, approximates the line length,
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and controls the Z-axis level to the display.
It sets and controls the duration of the Line Generator drawing period, which is either 4 pus
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or 19 ps, depending on the approximate line length.
It controls all display blanking.
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It multiplexes digital storage (Line Generator) X, Y, Z, and blanking with direct display of
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fast sweep, video, fast sweep Z, and retrace blanking.
Intensity level is modulated as a function of AX and AY. The Line Generator Z-Axis circuit
receives AX and AY from A3A3 Line Generator. The magnitudes of AX and AY are
summed together to approximate line length. The output of the Line Generator Z-Axis circuit
goes to the Bright circuit, which sets the Z-axis signal to maximum when bright lines are
drawn. The signal from the Bright circuit is multiplexed with the FSZ signal from A3Al
Trigger and becomes the Z signal to the display. The Z signal also goes to the AUX Z circuit,
where Z and AUX BLANK are combined to form the AUX Z signal.
The line length approximation form the Line Generator Z-Axis circuit goes to the Long Line
Comparator, which decides whether the line should be drawn as a long line (19 ps drawing
time) or a short line (4 ps drawing time). This decision is stored at the Input Register
and sent to the A3A3 Line Generator as the LLL signal. It goes with LGCLK to the Long
Line/Short Line Timing circuit, which generates the timing signals necessary to control the
Line Generator setup and drawing periods. The signal INTR is used by A3A6 Main Control
to determine when to send new X and Y values to the Line Generator. The timing signals also
go to the Integrator Switch Driver and to the Sample and Hold Driver, which form the drive
signals needed for the Line Generator.
Control of display blanking begins at the Input Register. Blank and blink information is held
in the register during the line drawing period. The Blanking Logic circuit controls all display
blanking. It unblanks, blanks, or blinks lines as required by the Input Register. It multiplexes
digital storage blanking with fast-sweep retrace blanking.
Fast Scan Trigger Detect and Bus Buffer circuits are used to provide information to A3A6
Main Control to create the digital storage display.
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