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The A3A8 Analog Digital Converter converts the analog video and sweep voltages to digital
data. Consequently, a failure on this assembly will affect the display of trace A and trace B
data. Character and graticule generation are not affected by A3A8.
Stuck bits in the Ramp Converter will distort the displayed signal. This is most easily
observed with slow sweep times. When a bit fails, the Ramp Converter will default to a 20 ms
sweep rate during the display period when that bit would normally be working. Figure 1-3 is
an example of the CAL OUTPUT signal with a 3 s sweep time when U5 pin 5 is struck low.
Center Frequency Readout will be 20.000 000 MHz for an
Note
HP 8568B/HP 8567A
I
By looking at noise with a 3 s sweep time (push Instrument Preset first), it is possible to
determine which of the data bits are stuck by counting the discrete states displayed. For
example, Figure 4 shows the result of an MSB failure (D9). 21°vg = 2 states are displayed.
To detect low order bit (DO-D4) failures, tune to the CAL OUTPUT signal and set frequency
span to 100 kHz, sweep time to 3 s. A failure will then result in slight "stair-stepping" of the
displayed signal. The noise display will be missing states, but this will be difficult to see.
Digital Storage Test Program 4 is used to verify the inputs to the DAC, U5. lf VRl is close to
the low end of its tolerance, VREF of DAC U5 may not be properly set.
Failures in the video analog to digital process are characterized by "stair-stepped" signals and
noise that is displayed as discrete vertical lines. Low order bit failures will cause many small
steps while a high order bit failure will cause a single step that will eliminate the peak of the
display. Note that only the signal will be affected and that the graticules and characters will
not be affected. Front panel displays of the CAL OUTPUT signal for several bit failures are
shown in Figures 5 and 6.
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C E N T E R 188.000 HtiZ
Figure 3. Ramp Converter Bit Failure
S P A N inn LHZ
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