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Memory Assembly A3A4 contains 4096 12-bit words of static random-access memory (RAM)
and 2048 8-bit words of read-only memory (ROM), plus the necessary latches, buffers, and
control logic for input and output operations. Data for display annotation (center frequency,
reference level, and so on.), graticules, characters, and TRACE A and TRACE B is stored in
memory.
Display Memory @
Display memory contains two 2 k x 12 blocks. The lower block, made up of U4 and U5,
corresponds to addresses 0000 through 2047 and is enabled by LCEl from Control Logic. The
upper block, U3 and U6, corresponds to addresses 2048 through 4095 and is enabled by LCE2.
Four of the eight input/output lines of U5 and U6 are not used since only 12-bit data words
are required. LOE enables the RAM outputs for read operations only. LWE writes data to
the RAM.
The RAM address latches, U7 and U8, store the memory address during read and write
operations. These latches are required because the memory address register is occasionally
changed before a read operation is completed. When not enabled, these latches are
transparent.
Memory Address Register @
Registers U15 and U16 store the memory address for display memory and character stroke
memory.
Memory Data Input Register @
Registers U9 and Ull store input data to be written to the display memory for write
operations only.
Buffers UlO and U12 pass data from Memory Data Input Register to display memory for
write operations only.
Memory Data Output Buffer @
Buffers U13 and U14 enable the output data from either display memory or character stroke
memory to the Digital Storage Bus for read operations only.
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