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true representation of noise are displayed on the CRT. This is accomplished by positive and
negative peak detection.
Positive Peak Detector @
The Positive Peak Detector acquires the most positive voltage to appear at its input and
holds that voltage on holding capacitor C26 until the circuit is reset by a reset pulse from the
decoding and timing circuits. FET Q6 is periodically turned on by the reset pulse, discharging
C26 through R12 and QS to ground. Figure 1 shows a simplified schematic of the Positive
Peak Detector.
Figure 1. Positive Peak Detector, Simplified Schematic
The circuit consists of amplifier Q3, Q2, Ql, diode CRl, holding capacitor C26, and buffer
Q4, Q5. When Ei, is less than the feedback voltage E,t, CR1 is off and C26 will hold the
voltage it has acquired. CR3 limits the reverse voltage across CR1 to minimize leakage
current. CR1 turns on when Ei, is greater than E out'
E
A pair of matched FETs, Q4A and Q4B, and emitter follower Q5 are used in the buffer
circuit. Q4A is used as a source follower and Q4B as a current source. The Q4A bias current
is equal to the algebraic sum of the current from Q4B, the base current to Q3B, and the bias
current through R13. This sum of currents insures a very small gate-to-source voltage and
prevents gate-to-source forward biasing.
as emitter followers and Q2 forming a differential pair. Gain for the differential stage is set by
collector resistor R7. Additional gain is provided by QlB. QlB is connected as a transistor
inverter with R9 in the emitter and R8 in the collector. QlA is connected as a diode. Gain
and offset adjustments for the Positive Peak Detector are performed in the resistor divider
that includes Rl and R2. GPOS potentiometer R39 adjusts the attenuation so that a 2 V
full-scale input produces a 1 V full-scale output. OFS POS potentiometer R44 zeroes the
and C26 charges to equalize Ei, and
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