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Fast Sweep Time Control @
Data on Instrument Bus lines 11 through 14 specify the fast sweep generator sweep time. This
data is latched into hex D flip-flop U6 when Address 51 is strobed. (Refer to the table, Note
6 on the schematic, for coding of the sweep time control lines.) Data on Instrument Bus line
15 is latched into U6 with the four sweep time bits (IOBll-IOB14) and enables fast sweep
generator operation.
Switchable Current Source
Current for the generation of the fast sweep ramp is supplied by Q13. Op amp U8 regulates
(through R6 and R7) the emitter voltage of Q13 to keep it equal to the reference voltage at
U8 pin 3.
which is made up of Rl, R2, and R3. The voltage difference between Q13 emitter and
across a switchable resistance between Q13 emitter and +15 VFl. FET switches Q7, QS, and
When Q7, QS, and Q9 are off, R14 sets Q13 collector current. In certain sweep times, Q9 is
turned on by U2C. (Refer to the table on the schematic, Note 6.) This places Rll in parallel
with R14, increasing the current by a factor of 5. Similarly, R12 or R13 may be switched in
to increase current by factors of 10 and 50 respectively. Q7, QS, and Q9 are controlled by
open-collector drivers U2B, U2A, and U2C. The FET switches are on when the FET gate
voltage is high (+15 V) and off when the FET gate voltage is low (approximately +0.2 V).
Fast Sweep Generator @
To produce the fast sweep ramp for sweep times 5100 /.Ls, current from Q13 charges timing
capacitor C4. For sweep times of 200 ps to 10 ms, Qll is turned on, placing timing capacitor
C5 in parallel with C4, increasing the sweep time by a factor of 100. C4 and C5 (if it is in the
circuit) are discharged by QlO and Q12 at the end of the sweep.
Discharge Switch
When no sweep is in progress, the output of open-collector inverter U7D is high (+5 V), and
current through R30 and R31 flow into QlO and through CR6 into Q12. In addition, current
flows from Q13 into Q12. At the start of a fast sweep ramp, U7D pin 8 goes low, and the
voltage at the anode of CR6 and the emitter of QlO is pulled slightly negative by R32. CR6
becomes reverse biased, and QlO turns off, turning Q12 off. Current from the collector of Q13
now flows into timing capacitors C4 and C5, and the sweep ramp begins. When the end of
the sweep ramp (+2.2 V) is detected by the Fast Sweep Control circuit, U7D pin 8 goes high
(about +5 V), turning QlO on. This turns Q12 on, and it begins to discharge C4 and C5.
Q12 continues to discharge the timing capacitors until CR6 becomes forward biased. At that
time, the circuit reaches equilibrium, holding the sweep ramp at near 0 V, with the offset
adjusted by R34.
Fast Sweep Buffer Amplifier
Op amp U14 is connected as a unity gain buffer amplifier, which provides the low impedance
fast sweep ramp output (FS OUT). FS OUT is applied to the X-axis scan multiplexer in
4 A3A1
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