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begin a conversion, the ADC is first reset to ones by a low HOLD. When HOLD goes high,
each bit is individually tried in a "trial" conversion, starting with the most significant bit. A
decision is made to retain or drop the bit based on the comparator output. Once the decision
has been made for each of the 10 bits, a "conversion-complete" signal sets the flip-flop U14A.
This signal, called BUSY, can be transferred onto the Digital Storage Bus by the BUS Buffers
u15.
Ramp Converter @
The Ramp Converter makes a comparison between the analog sweep signal and the scan
address (X Axis). Comparator Ul makes this comparison and produces a signal called RAMP.
RAMP high indicates that the scan address needs to be updated. When RAMP is low, no
update is needed. When an update occurs, a new address is latched into the Scan Address
latches U9 and UlO. This results in an updated comparison between the output of DAC U5
and the Sweep input as shown in the simplified schematic (Figure l-2). A reference voltage is
created for the DAC by VRl and U3. This voltage is adjustable by R5 to set the full-scale
trace. Amplifier U2 sums the currents from the DAC U5, the sweep input, and ZERO stick,
and drives the comparator input. OFFS is adjustable by R6.
SWEEP
SECT 1 ON)O-1 ov
REF
G A I N
2 A3A8
SUMMING AMP
SCAN ADDRESS
LATCHES
Figure 2. Ramp Converter, Simplified Schematic
u 1 5 __<
COMPARATOR
T E S T B I T
BUFFER
NEW SCAN ADDRESS
WHEN UPDATED
RAMP
( S T
T
A
U S
INFORMATION
T O D I G I T A L
STORAGE BUS)
FROM
D I G I T A L
< S T O R A G E B U S
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