Table of Contents
Advertisement
The program addresses decrements in a binary sequence through all possible addresses with
the BS line toggling at 4 MHz, SO at 2 MHz, Sl at 1 MHz, and so on. This checks the A3A6
Main Control assembly, its ROM, Pipeline Registers, flip-flops and control pulses outputs, and
the A3A7 I/O Port Decoder. To check the System ROMs, the same test setup is used but the
This test requires that the 8 MHz clocks, CLK and LCLK, and the initialize signal, LTON
from A3A7, be working.
This test also requires that a basic "kernel" be running. This includes part of the State
Machine Control (F) and the loop consisting of the Link Register, State Register, and Branch
Length Adder on A3A6. See "A3A6 Main Control, Troubleshooting" to troubleshoot this
circuitry.
Test Program 1
This program generates the pattern to test the A3A5 Data Manipulator, its Accumulator,
Control Decode logic, Pipeline Registers, and parts of its ALU, Constant ROM, and
Multiplexer Bus Drivers. This is the test that exercises the Digital Storage Bus with all
feedback from it disabled.
Test Program 2
This program is the same as Test Program 1 except that the Register RAM outputs are
enabled on the A3A5 Data Manipulator assembly. Since there is now feedback from the
Accumulator through the Register RAM, a bad bit will make all higher order bits appear bad;
so when probing the bus lines, the low order bits should be verified first and then higher order
ones. The program generates various patterns that are written into and read from register
RAM location 0; it also selects all the qualifier inputs on A3A7 in both a low and a high state;
and it exercises all the bits in the branch length word on the A3A6 Main Control assembly.
This program is used to verify the Branch Length Adder on A3A6 Main Control assembly
when A3A6El jumper is replaced. On A3A5 it tests the Register RAM, ALU A inputs, and
the multiplexer inputs from the RAM
Test Program 3
This program uses the Register RAM location 0 and the qualifier verified in Test Program 2
to generate a complete pattern test of all the Register RAM locations and Constant ROM
4 A3
disables interrupt and return inputs to the State Machine
Controller. The BS (Block Switch) line is forced to toggle at a
4 MHz rate.
disables qualifier feedback.
forces state machine interrupt high.
disables the Register RAM outputs.
disables qualifier feedback.
forces state machine interrupt high.
. And finally, it checks the qualifier select circuitry on
S
test qualifier bit read by program.
the long line threshold on A3A2 is adjusted fully
clockwise so that the normal interrupt, INTR, is always
a 20 ps period, independent of the line generator.
Advertisement
Table of Contents
