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output with 0 V input. U5 compares the input and output of the Peak Detector. A TTL high
level is produced when the output is greater than the input. (R40, R41, and R16 provide a
small amount of hysteresis for noise immunity.)
Negative Peak Detector @
The Negative Peak Detector acquires the most negative voltage to appear at its input and
holds that voltage on holding capacitor C38 until reset by a pulse from the decoding and
timing circuits. Circuit operation is the same as that of the Positive Peak Detector except
that supply polarities are reversed and PNP instead NPN transistors are used. Figure 2 shows
a simplified schematic of the Negative Peak Detector.
F R O M A4A1
Figure 2. Negative Peak Detector, Simplified Schematic
The circuit consists of amplifier Q7/Q8/QlO, diode CR2, holding capacitor C38, buffer
of Q9. This insures that the voltage across C38 is always negative for positive outputs from
0 V to +1 V. GNEG potentiometer R52 sets the gain (input attenuation) so that a 2 V
full-scale input produces a 1 V full-scale output. OFS NEG potentiometer R36 zeroes the
offset. U4 compares the input to the output.
Decoding and Timing @
The Decoding and Timing circuit provides reset pulses to the Peak Detectors and control lines
for Multiplexer selection, and it performs other logic functions.
After inversion by U8A, U8B, and U8C, the voltage levels are shifted to -0.5 V and +9 V.
Multivibrators U12A and U12B produce pulses (when triggered by HOLD) which reset the
Peak Detectors. Latches U13A and U13B are used to provide the Peak Detector status signal
LTRK.
Multiplexer @
The outputs of the Peak Detectors are multiplexed through Ul before sampling by the Track
and Hold circuit. Control lines to the Multiplexer are provided by the Decoding and Timing
circuit.
2 A3A9
R 2 0
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