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Hold into storable digital data for A3 Digital Storage. The important data and control lines
are: all Digital Storage Bus bits, BO-Bll, which are used for data inputs and outputs, ADC,
which loads final ADC data onto the Digital Storage Bus; HOLD, which resets the ADC and
initiates a conversion; LD RMP, which updates the Ramp DAC with a new scan address; and
LTSTA, which enables test bits (BO, Bl, and B2), RAMP, LTRK, and BUSY onto the Digital
Storage Bus.
ADC @
The ADC (analog-to-digital) circuit converts analog (sampled video) data from A3A9 Track
and Hold onto 10 bits of binary code using the technique of successive approximation. A
simplified schematic of the ADC circuit is shown in Figure l-l.
Figure 1. A3A8 Analog-Digital Converter, Simplified Schematic
The ADC circuit consists of digital-to-analog converter (DAC) Ull, comparator U12, and
successive approximation register U13. A 1 MHz clock fixes conversion time at 11 ps. To
OUTPUT
HOLD
' B U S Y '
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