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The Digital Storage Processor is controlled by an algorithmic state machine, which uses
relative-state addressing and interrupt linkage in performing the control algorithm. The
Digital Storage Processor includes A3A4 Memory, A3A5 Data Manipulator, A3A6 Main
Control, and A3A7 Interface.
State Register @J
The State Register, U13 and U14, contains the present state of the algorithm. The present
state data is supplied to the Program ROM (Read-Only Memory), where it is decoded into
control functions.
Branch Length Adder @
The Branch Length Adder, Ul and U2, receives branch length data from the Program ROM
and adds it to the present state data to generate the next state.
Link Register @
The Link Register, U12 and U15, holds the suspended state of the main program during
interrupts and holds the next interrupt state during the main program.
In effect the Link Register acts as a "bookmark" for both the main program and the interrupt
program, so that either program can resume at the correct state.
State Machine Control @
The State Machine Control, U16, U17, U18, U27C, and U27D, manages switching between
the main and interrupt programs. In addition, it generates a signal to increment the Branch
Length Adder for conditional branching.
Program ROM @
The Program ROM, U4, U6, U8, and UlO, contains both the main program and the interrupt
program. U5, U7, U9, and Ull are test firmware used to generate diagnostic tests.
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