Video Controller - Tandy 1000 SL Technical Reference Manual

Interrupts 0 and 1 are connected to system board functions as
indicated in the chart. Interrupts 2-7 are connected directly to
the Expansion Bus, with the normal assigned functions listed in
the chart.
Video Controller
The next major block of the Tandy 1000 SL is the video interface
circuitry. This custom part contains all the logic necessary to
generate an IBM-compatible color video display. The video
interface logic consists of the 100-pin custom video circuit
(U26), four 64K X 4 DRAMS (U6, U7, U8, and U9), a 74LS273 latch
(U141, a 16K X 8 character ROM, and associated logic for
generating RGBI or Monochrome video.
The Tandy 1000 SL video interface circuitry controls 128K of
memory. This DRAM is shared by the CPU and the video. Normally,
the video requires only 16K or 64K for the video screen, and the
remainder of the 128K is available for system memory use.
The Tandy 1000 SL video interface custom circuit is composed of a
6845 equivalent design, dynamic RAM address generation/timing,
and video attribute controller logic.
Normal function of the video interface custom circuit is as
follows. After the 6845 is programmed with a correct set of
operating values, a 6:l multiplexer generates the address inputs
to the dynamic RAMS. This MUX switches between video (6845)
address and CPU address as well as between row and column
address. Also, the video interface chip provides the RAM timing
signals and generates a wait signal, VIDWT-, to the CPU for
proper synchronization with the video RAM access cycles.
The outputs from the RAM chips are only connected to the video
interface custom circuit, so all CPU read/write operations are
buffered by this part. During a normal display cycle, video data
from the RAM chips is first latched in the Video Attribute latch
and the Video Character latch. The video interface requires a
memory organization of 64K X 16 and latches 16 bits of memory
during each access to RAM. From the output of the two latches,
the data is supplied to the character ROM for the alpha modes or
to the shift registers for the graphics modes. A final 2 : l MUX
switches between foreground or background in the alpha modes.
From the 2:l MUX, the RGBI data is combined with the PC color
select data and latched in the Pre-Palette latch. This latch
synchronizes the RGBI data before it is used to address the
Palette. The Palette mask MUX switches between incoming RGBI data
and the Palette address register. During a CPU write to the
Palette, this address register selects one of the 16 Palette
locations. Also, the Palette mask MUX allows any of the input
RGBI bits to be set to zero.
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