Tandy 1000 SL Technical Reference Manual page 33

IRQ2 through IRQ7 (B4, B21-B25). These signals are used to tell
the CPU that an 1/0 device needs attention. The Interrupt
Requests are prioritized with IRQ2 having the highest priority
and IRQ7 the lowest.
An
Interrupt Request is generated when any
IRQ signal is driven high and held high until the CPU
acknowledges the interrupt.
IOR- (B14). IOR- is a read signal that instructs an 1/0 device to
drive its data onto the data bus (IODO-IOD7). This line can be
driven by the CPU Control IC or by the DMA controller. IOR- is
active low.
IOW- (B13). IOW- is a write signal that instructs an 1/0 device
to read, or latch, the data from the data bus (IODO-IOD7). This
line can be driven by the CPU Control IC or by the DMA
controller. IOW- is active low.
MEMR-
(B12). MEMR- is a read signal that instructs a memory
device to drive its data onto the appropriate data bus (IODO-
IOD7). This line can be driven by the CPU Control IC or by the
DMA controller through the CPU Control IC. MEMR- is active low.
MEMW- (Bll). MEMW- is a write signal that instructs a memory
device to read, or latch, the data from the appropriate data bus
(ADO-AD15 for 16-bit memory, IODO-IOD7 for 8-bit memory). This
line can be driven by the CPU Control IC or by the DMA controller
through the CPU Control IC. MEMW- is active low.
DRQ1, DRQ2, and DRQ3 (B18, B6, B16). These lines are
asynchronous DMA requests by peripheral devices to gain DMA
service. They are prioritized with DRQl having the highest
priority, DRQ2 next, and DRQ3 lowest. A DMA request is generated
by driving a DRQ line active high and holding it until the
corresponding DACK (DMA acknowledge) signal goes active. DRQ1,
DRQZ, and DRQ3 perform only 8-bit transfers. All DRQ lines are
active high.
DACK1-, DACK2-, and DACK3-, B17, B26, B15). These lines are DMA
acknowledge signals used to acknowledge DMA requests DRQ1, DRQ2,
and DRQ3. All DACK signals are active low.
REFRSH- (B19). This signal is used to indicate a refresh cycle
that can be used by a memory board to refresh Dynamic memory.
REFRSH- is active low and 4 cycles are generated every 62.5 usec.
DMATC (B27). DMATC is a signal that provides a pulse when the
terminal count for any DMA channel is reached. DMATC is active
high.
14MHz (B30). 14 MHz is an oscillator signal that is a high-speed
clock with a 70 nanosecond period (14.31818 megahertz). It has a
50% duty cycle.
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