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w
Register
8237A
Operatlon
Command Register
Command
Mode
Request
Mask
Mask
Temporary
Status
7
0
6
4
l l - n
Write
Write
Write
SetIReset
Write
Read
Read
1
1
L
(
0
DACK
renw active
iOw
1
DACK
renw
active
high
231466-5
Mode Reaister
-
00
01
10
11
00
V o r l f y t n n r f r
0 1
Write
lnnrkr
1 0
Read tranrfer
11 111ega1
4
XX
If blt8
6
.nd 71 11
1
{
0
Addrerr increment wiect
t
Address decrement wlect
00
Demand mode nelect
0 1
Slngle mode rdect
1 0
Block mode reiect
11
Cascade
mode relect
231466-6
Request Reaister
7
6
6
4
3 2 1
0 t - B l t N u n b n
00
Select channel
0
0 1
Select channel t
1 0
Select channel 2
I
( 0
Rawtrequestblt
1
Sat requert
blt
231 486-7
Mask Register-Each channel has associated with
it a mask bit which can be set to disable the incom-
ing DREQ. Each mask bit is set when its associated
channel produces an
if the channel is not pro-
grammed for Autoinitialize. Each bit of the 4-bit
Mask register may also be set
or
cleared separately
under software control. The entire register is also set
by a Reset. This disables all DMA requests until a
clear Mask register instruction allows them to occur.
The instruction to separately set or clear the mask
bits is similar in form to that used with the Request
register. See Figure
5
for instruction addressing.
7
0
0
4
3 2
1
O C - B l l N u m k r
00
S O k t channel 0 mMk bit
0 1
SqlWt channel
1
w k blt
1 0
SOl O Ct channel
2
mMk blt
11
Select channel
3
w k bit
0
Clear meek blt
1
Set mark blt
231466-8
All four bits of the Mask register may also be written
with a single command.
7
0
6
4
3
2
1 Of-BllNumbu
0
CleU
ChWbIlOl
0 mMk bll
Don't
Cue
1
SOt
channel 0
mark blt
0
Clwr channel 1 m k blt
1
Set channel
1 m u k
blt
0
Cleu channel
2
mark
blt
1 a t ChMnOl2 mMk bit
[
0
CIOU
channel
3
mark bit
t
Set channel 3 mark bit
231468-8
I
I
0
1
0
1
0
0
0
0
1
0
1
0
1
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
1
1
1
0
0
1
1
1
0
1
0
0
1
1
0
0
0
Figure 5. Deflnition of Register Codes
Status Register-The Status register is available to
be read out of the 8237A by the microprocessor. It
contains information about the status of the devices
at this point. This information includes which chan-
nels have reached a terminal count and which chan-
2-241
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