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1
I
2
I
3
I
4
PIN DESCRlPTlON
:zit
ground potenti.
*5V power supply during operaticn. programming
and verification.
Port
0
port
0 is an Ebit
open
drain bidirectional 1 1 0 port.
It is
also
the
multip)a*ed brrorder address and data
bus when using extern4 memory. It
is
used for data
input . n d
output
during
progunming and verifica-
"cc
t i o h P O C t O M r i n k h a r r C
w o r n r e
Port1
Port 1 is
an
Ebit quai-bibireaimal
I 1 0
port. It
is
urc6
for the loworder
rddrca
byte during program-
ming and verification. Port 1
u n
sinlrh0Urc.e
one
m
load.
Port2
Port 2
is an Ebit quasi-bidirutiod
I x ) port
It
rtro
emits
t h e
highorder8
bitsol
adOmss*ha
-
external
memory. It is used forthehiphadcr rddrass;
and
the
control signals during pmgrrmming
and
mification. port
2
can
sin-rce
one
m
m.
Port3
Port
3 i s
an
&bit quai-bidirectional VO
pon
It
.Ita
contains the interrupt. timer.
saria~
port and
Ri5
and
WR
pins
that
am
used
various options.
out-
put latch comsponding to a special function m-
be
programmed to a one
(1)
for mat function
t o
operate. Port
3
can
ink/source
one TlL
load.
The
special functions are assign& to the pins of
3 .
as
follows:
-RXO/data (P3.0). %rial port's receiver data input
(asynchronous) or data inputloutput (synchro-
W S ) .
outpul (asynchronous)
o r
clock output
(synchm-
nous).
-INTO (P3.2). Interrupt 0 input
or gate control
input
for counter 0 .
--INT1
(~3.3). Interrupt
1
input or gate control
input for counter 1.
-lU
( P 3 . 4 ) .
Input to counter 0.
-11
(P3.5).
Input to counter 1 .
-
WR (P3.6). The write control signal latches the
data byte from
Port
0 into the External Data
Memory.
-m
( P 3 . 7 ) .
The
mad control signal
enables
External
Data Memory to Port 0.
RSTNPD
-lXD/cloCk
(P3.1).
Serial
port's transmitter
data
-
-
A
low to high transition
00
this pin (at approximately
3V) resets the 8051. If VPD is held within its spec
(approximately 4V). while VCC drops below spec.
Vpo will provide standby power to the
RAM.
When
V p g is low. the RAM'S current is drawn from
Vcc.
A small internal resistor permits poweron
reset
using only a capacitor connected to Vcc.
Provides Address Latch Enable output used
for
latching the address into external memory during
normal operation.
R
e
the program pulse
input during EPROM programming.
The Program Store
EnrMc
output is a control signal
that enades the external Program Memory to the
bus during normal tcccn operations.
When held at a TIL high level. the 8051 executes
instructions from the internal ROMlEPROM when
the PC is less than
4 0 9 6 .
When held at a
l T L
low
level. the 8051 fetches all instuctions from external
Program Memory. The pin also receives the 21V
EPROM
programming supply voltage.
XTALl
Input to the oscillatoh high gain amplifier.
A
crystal
o r
external source can be used.
X T A U
Output from the oscillator's amplifier. Required when
a cryrtal is used.
ALwPROG
PSEN
=DO
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