Tandy 1000 SL Technical Reference Manual page 130

DESIGN CONSIDERATIONS
1.
Cascading from channeizero. When using mul-
tiple 8237s, always start cascading with channel
zero. Channel zero of the 8237 will operate incor-
rectly if one or more of channels 1, 2, or 3 are
used in the cascade mode while channel zero is
used in a mode other than cascade.
2. Do not treat the ORE0 signai as an asynchro-
nous input whiie the channel is in the "de-
mand" or "cascade"modes. If DREQ becomes
inactive at any time during state s4, an illegal
state may occur causing the 8237 to operate im-
properly.
3. HRQ must remain active untii HLDA becomes
active. If HRQ goes inactive before HLDA is re-
ceived the 8237 can enter an illegal state causing
it to operate improperly.
4. Make sure the MEMR# iine has 50 pF loading
capacitance on it. When doing memory to mem-
ory transfers, the 8237 requires at least 50 pF
loading capacitance on the MEMR+ signal for
proper operation. In most cases board capaci-
tance is sufficient.
5. Treat the READY input as a synchronous in-
put. If a transition occurs during the setup/hold
window, erratic operation may result.
DATA SHEET REVISION REVIEW
The following list represents key differences be-
tween this and the -002 data sheet. Please review
this summary carefully.
1. Major cleanup on the "NOTE" sections of this
data sheet.
a. Pin 5 no longer references a note. It is now
included in the pin description area under the
name "PIN5".
b. The note placed in the "typical" section of the
D.C. Characteristics table is now referenced to
a note section included with that table.
c. Notes in the A.C. Characteristics table have
been renumbered and are included in a notes
section for the A.C. Characteristics.
d. The note that was previously referenced in the
A.C. TESTING INPUT/OUTPUT WAVEFORM
diagram has been replaced with the actual
note.
e.
The note that was previously referenced in the
SLAVE MODE WRITE TIMING diagram has
been included in a "NOTE" section with the
diagram.
f. The note that was previously referenced in the
SLAVE MODE READ TIMING diagram has
been included in a "NOTE" section with the dia-
gram.
g. The note that was previously referenced in the
DMA TRANSFER TIMING diagram has been
included in a "NOTE" section with the diagram.
2. A "Design Considerations" section was added to
alert designers to certain design aspects of the
8237.
3. The timing parameters TAR for the 8237A-4 and
8237A-5 have been changed from 50 ns to 0 ns.
2-252