Nmi Logic 1; 8087 Control Logic; Data Buffers And Conversion Logic - Tandy 1000 SL Technical Reference Manual

NMI Logic
In the Tandy 1000 SL, the Non-Maskable Interrupt (NMI-1 indicates
an 1/0 error condition, or Numerical Math Coprocessor 8087 error
condition. Both error conditions are being generated internal to
the 8079024 custom IC.
8087 control Logic
The 8087 Numerical Coprocessor is connected to the 8086 address
and data lines in parallel. The 8087 will monitor the 8086 CPU
status (SO-S2) and Queue status (QSO-QSl) in order to decode
instructions in synchronization with the CPU. For
resynchronization, the 8087 NPBUSY signal is used to tell the CPU
that the 8087 is executing an instruction. The 8087 also has the
capability of informing the 8086 of an error or exception by
using the NPINT signal. This signal is sent to the 8079024 custom
IC which then generates the proper codes to the 8086. The 8087
will use the
RQ/GTO-
signal to gain control of the bus for data
transfers.
CPU Address Buffers
The 8079024 custom IC provides the buffering of the address lines
to the system. AO-Al9 are buffered and latched for the expansion
bus slots and 1/0 peripherals. ALE is used to latch AO-A11
internal to the 8079024 custom IC and CPUALE is used to latch
A12-Al9 externally. The addresses are held for the complete bus
cycle. AO-A19 are also used to address the BIOS ROMS and DRAM/DMA
Control. The multiplexed address lines MAO-MA8 are also generated
and buffered to the DRAM memory by the 8079024 custom IC.
Data Buffers and Conversion Logic
The 8079024 custom IC provides the data buses, buffers, and
drivers for DO-Dl5 to the system. Two data buses are generated,
IODO-IOD7 for the expansion bus slots, and
ADO-AD15,
which is
routed to the 8086 CPU, 8087 Coprocessor data bus, ROM, and DRAM.
The direction and control of the data buffers are provided
internal to the 8079024 custom IC. Conversion logic is also
implemented in the 8079024 custom IC. This conversion logic
allows data to be transferred from the lower to upper or upper to
lower data byte to meet the requirements of the CPU or receiving
device.
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