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1/0
Decode
The 8079024 custom IC accomplishes the 1/0 Address decoding. This
IC provides all the necessary chip select signals to the system.
The DECO-, DEC1-, and DEC2- output signals of the 8079024 custom
IC are encoded device select lines that are fed directly to the
KFIT custom IC (u30) and 8079021 custom IC ( ~ ~ 4 0 1 , in which 1/0
address decoding is generated.
Floppy Disk Controller
The on-board Floppy Disk Controller (FDC) and KFIT custom IC
(U30) interface the system to the Floppy Disk Drive (FDD). Up to
two internal Sf-inch 360K or one 5)-inch
and one 33-inch FDDs can
be accommodated.
The FDC circuit can be organized into the following subsections:
.
uPD765A FDC Chip
System Interface
Clock Generation
Precompensation
Data Separator
Disk Drive Interface
uPD765A Chip. The uPD765A FDC chip (EU4) integrates most
control logic necessary to:
.
interface the serial bit stream to or from the FDD to
parallel bus of the system
.
implement the commands necessary to operate the FDD
of the
the
.
maintain information about the status of the FDD
During a read or write data operation to the FDD, the FDC chip
generates a DMA request for a byte transfer to or from memory.
The FDC chip continues to generate DMA requests until the
preprogrammed amount of data is transferred as signified by
generation of a Termination Count (DMATC) Signal. After the DMATC
is reached, the FDC chip generates an interrupt to the system
through INT so that status and result data can be serviced.
System Interface. Various ICs, along with the KFIT custom IC,
latch and buffer data to and from the system.
A
DOR Write
(Digital Output Register) is generated on an 1/0 write to Port
3F2 (hex). This signal latches the data byte that is bit defined
as the Drive Select, DSO-, DS1-, and DS2-, Motor On, MTRON-, DMA,
(FDCDRQ), Interrupt Request (FDCINT), and a reset signal
(FDCRST-1 to the FDC controller U12.
13
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