Tandy 1000 SL Technical Reference Manual page 185

Internal Registers
The pPD765AlpPD7265 contains two registers which
may be accessed by the main system processor: a sta-
tus register and a data register. The
&bit
main status
registercontains the status information of the FDC, and
may be accessed at any time. The &bit data register
(which actually consists of four registers, STO-ST3, in a
stackwith onlyone register presented to thedata busat
a time), stores data, commands, parameters, and FDD
status information. Data bytes are read out of, or written
into, the data register in order to program or obtain the
results after a particular command (table
3).
Only the
status register may be read and used to facilitate the
transfer of data between the processor and pPD765Al
pPD7265.
The relationship between the statusldata registers and
the signals RD, WR, and
A0
is shown in table 1 .
Table 1. StatuslData Register Addressing
b E W R
r M o t k n
0 0 1 Read main status register
0 1 0 Illegal
0 0 0
llleaal
1 0 0 Illegal
1
0 1 Read from data register
1 1 0 Write into data register
The bits in the main status register are defined in
table 2.
Table 2. Main Status Register
mn
Ik. wlnw FUnctkn
OB0 DoB
FDD number 0 is in the seek mode. If any
of
the DnB bits is set FDC will not accept
read or write command.
DB1 D1B FDDnumberlisintheseekmode. lfanyof
the D, B bits is set FDC will not accept read
or write command.
FDD number 2 is in the seek mode If any
of the D, B blts is set
FDC will not accept
read or wrlte command.
(FDD 0 Busy)
(FDD 1 Busy)
DBp
DpB
(FDD 2 Busy)
DE3 D3B
FDD number 3 is in the Seek mode. If any
of
the DnB bits is set FDC will not accept
read or write command.
DB4 CB
A Read or Write command is in process.
FDC will not accept any other command.
DB5
EXM This bit is set only during execution phase
in non-DMA mode. When
DB5
goes low,
execution phase has ended and result
phase has started. It operates only during
non-DMA mode of operation.
(FOD 3 Busy)
(FDC Busy)
(Execution Mode)
Table 2. Main Status Register (cont)
Pln
no.
wlnw Function
DBg
DIO Indicates direction of data transfer be-
(Data Input/Oulput) tween FDC and data register If DIO=l.
then transfer
IS
from data register to the
processor if DIO=O. then transfer is from
the processor to data register
DB7
ROM Indicates data register is ready to send or
(Request for Master) receive data to or from the processor Both
bits DIO and ROM should be used to per-
form the hand-shaking functions of
"ready" and "direction" to the processor
The DIO and RQM bits in the status register indicate
when data is ready and in which direction data will be
transferred on the data bus. The maximum time be-
tween the last or
WR
during a command or result
phase and DIO and RQM getting set or reset isl2ps. For
this reason every time the main status register is read
the CPU should wait 1 2 p ~ T h e maximum time from the
trailing edge of the last RD in the result phase to when
OB4
(FDC busy) goes low is 12ps. See figure 1.
Fiaure 7. DIO and RQM
o m " ,
A-
D m
register ready lo
+x
wdlten Into by pmessoi.
6-
Data
~ l s l e r 1101 ready 10 be written
Info
by pmcessor.
C- Data register
m d y
for nad dala byte to
be read
by pmcessor.
P Data register not
ready
Io +x
read by
pmcessror.
6-1 0