Tandy 1000 SL Technical Reference Manual page 116

ACTIVE CYCLE
When the 8237A is in the Idle cycle and a non-
masked channel requests a DMA service, the device
will output an HRQ to the microprocessor and enter
the Active cycle. It is in this cycle that the DMA serv-
ice will take place, in one of four modes:
Single Transfer Mod-In Single Transfer mode
the device is programmed to make one transfer only.
The word count will be decremented and the ad-
dress decremented
or
incremented following each
transfer. When the word count "rolls over" from zero
to FFFFH, a Terminal Count (TC) will cause an Auto-
initialize if the channel has been programmed to do
so.
DREQ must be held active until DACK becomes ac-
tive in order to be recognized. If DREQ is held active
throughout the single transfer, HRQ will go inactive
and release the bus to the system. It will again go
active and, upon receipt of a new HLDA, another
single transfer will be performed. In 8080A, 8085AH,
8088,
or
8086
system, this will ensure one full ma-
chine cycle execution betwaen DMA transfers. De-
tails of timing between the 8237A and other bus
control protocols will depend upon the characteris-
tics of the microprocessor involved.
Block Transfer Mod-In
Block Transfer mode the
device is activated by DREQ to continue making
transfers during the service until a TC, caused by
word count going to FFFFH,
or
an external End of
1Sf LEVEL
-
HRO
DREO
C -
-
HLDA DACK
-
Process
(m)
is encountered. DREQ need only be
held active until DACK becomes active. Again, an
Autoinitialization will occur at the end of the service
if the channel has been programmed for it.
Demand Transfer Mode-In Demand Transfer
mode the device is programmed to continue making
transfers until a TC or external is encountered
or until DREQ goes inactive. Thus transfers may
continue until the
I 1 0
device has exhausted its data
capacity. After the I/O device has had a chance to
catch up, the DMA service is reestablished by
means of a DREQ. During the time between services
when the microprocessor is allowed to operate, the
intermediate values of address and word count are
stored in the 8237A Current Address and Current
Word Count registers. Only an
m
can cause an
Autoinitialize at the end of the service. is gener-
ated either by TC or by an external signal. DREQ
has to be
low
before S4 to prevent another Transfer.
Cascade Mode-This mode is used to cascade
more than one 8237A together for simple system
expansion. The HRQ and HLDA signals from the ad-
ditional 8237A are connected to the DREQ and
DACK signals of a channel of the initial 8237A. This
allows the DMA requests of the additional device to
propagate through the priority network circuitry of
the preceding device. The priority chain is preserved
and the new device must wait for its turn to acknowl-
edge requests. Since the cascade channel of the
initial 8237A is used only for prioritizing the addition-
al device, it does not output any address or control
8257A
HRO
HLDA
MICROPROCESSOR
W t A
DREO
DACK
-
HA0
-
HLDA
-
ADDITIONAL
DEVICES
231468-3
Figure 4. Cascaded 8237As
2-238