Expansion Bus Signal Description - Tandy 1000 SL Technical Reference Manual

Expansion Bus Signal Description
The following signal descriptions for the System 1/0 Bus are for
PC bus-compatible option cards. Note that all signal lines are
TTL compatible levels and that 1/0 adapters should be designed
with a maximum of two low power Shottky (LS) loads per line.
BCPUCLK (B20). BCPUCLK is the System clock and has a period of
125x1s in 8 MHz mode, or 25011s in
4
MHz mode. It has a 50% duty
cycle and is used only for synchronization with the CPU. It is
not intended for uses requiring a fixed frequency.
A0 through A19 (A12-A31). These lines are 20 address bits used to
address memory and 1/0 devices within the Tandy 1000 SL. They are
gated on the system bus when the BUSALE signal is high and are
latched on the falling edge of the BUSALE signal. Generation of
these signals is accomplished by the CPU or a DMA controller. AO-
A19 are active high.
BUSALE (B28). BUSALE is a Buffered Address Latch Enable generated
by the CPU control IC. It is used to latch valid addresses from
the CPU, and can be used by an I/O board to indicate a valid CPU
address, in conjunction with HLDA. BUSALE is active high.
HLDA (All). HLDA is an Address Enable signal used to remove the
CPU and other devices from the bus to allow DMA transfers to take
place. During HLDA active, the DMA controller has control of the
address bus, the data bus, the READ command lines, and the WRITE
command lines. HLDA is active high.
IODO through IOD7 (A2-A9). These signals are the data bus 1/0
Bits 0 through 7 from the CPU to memory and
1/0
devices on the
bus. IODO is the least significant bit (lsb), and IOD7 is the
most significant bit (msb).
BRESET (B2). BRESET is used to reset or initialize the expansion
logic during power-up time, line voltage outage, or when the
Reset switch on the front panel is pressed. BRESET is active
high.
NMI- (All. This signal indicates an uncorrectable system error
when active. The NMI- signal provides the system board with
parity information about memory or devices on the bus. NMI- is
active low.
IOCHRDY (A10). This signal is used to lengthen
1/0
or memory
cycles when driven low by the active device. (This signal should
not be held low more than 15 microseconds.) Any slow device using
this line should drive it low immediately upon detecting its
valid address and a READ or WRITE command. See the timing diagram
for setup times. IOCHRDY is active high (Ready condition).
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