Tandy 1000 SL Technical Reference Manual page 179

pPD765A/7265
NEC
Ordering Information
P8d
Max Frsq.
Number
PlCk8pC
Typo Ol Opsritinn
pPD765AC, pPD765AC-2 40-pin plastic DIP
8 MHz
pPD7266C. pPD7265C-2 &pin plastic DIP 8 MHz
Pin Identification
Ilo.
srnaoi
FUnctkn
1 RESET Reset input
2 Read control input
RD
3 W R Write control input
4
w
Chip select input
5 A0 Data or status select input
-
-
6-13 DBo-DB7 Bidirectional data bus
14 DRQ DMA request output
15 DMA acknowledge input DACK
16 T C Terminal count input
17
I DX
Index input
18 I NT Interrupt request output
-
19 CLK Clock input
20 GND Ground
21 WCK Write clock input
22 ROW Read data window input
-
23 ROD Read data input
24 VCD VCD sync output
25 WE Write enable
O U ~ O U ~
26 M FM MFM output
27 HD Head select output
28. 29 USo, US1 FDD unit select output
31,32
Bo.
PSI Preshift output
30 WDA Write data wtput
33 FLT I TRo Faultltrack zero input
34 WP/TS Write protectltwo side
35 ROY Ready input
36 HDL Head load output
37 FRISTP Fault reset/ step output
input
38 LCTIDIR Low current direction
39 R W I SEEK Readlwritelseek output
output
40
vcc
D C p e r
Pin Functions
RESET (Reset)
The RESET input places the FDC in the idle state. It re-
sets the output lines to the FDD to 0 (low). It does not
affect SRT, HUT, or HLT in the Specify command. If the
RDY input is held high during reset, the FDC will gener-
ate an interrupt within 1.024ms. To clear this interrupt,
use the Sense Interrupt Status command.
m(Read Strobe)
The m i n p u t allows the transfer of datafrom the FDC to
the data bus when low. Disabled when CS is high.
m ( W r i t e Strobe)
The
WR
input allows the transfer of data tothe FDC
from the data bus when low. Disabled when CS is high.
&(Data/Status Select)
The
A0
input selects the data register (A0
=
1) or status
register
(A0
=
0) contents to be sent to the data bus.
CS (Chip Select)
The FDC is selected when
and Ao.
DBo-DB7 (Data Bus)
DBo-DB7 are a bidirectional 8-bit data bus. Disabled
when CS is high.
DRQ (DMA Request)
The FDCasserts the DRQoutput high to request a DMA
transfer.
DACK (DMA Acknowledge)
When the
the controller is performing a DMA transfer.
-
is low, enabling
m,
m,
_.__
input is low, a DMA cycle is active and
6-4