Tandy 1000 SL Technical Reference Manual page 117

w
0237A
signals of its own. These could conflict with the out-
puts of the active channel in the added device. The
8237A will respond to DREQ and DACK but all other
outputs
except HRQ will
be
disabled. The ready in-
put is ignored.
Figure
4
shows two additional devices cascaded into
an initial device using two of the previous channels.
This forms a two level DMA system. More 8237As
could
be
added at the second level by using the
remaining channels of the first level. Additional de-
vices can also be added by cascading into the chan-
nels of the second level device, forming a third level.
TRANSFER TYPES
Each of the three active transfer modes can perform
three different
types
of transfers. These are Read,
Write and Verify. Write transfers move data from an
I10 device to the memory by activating and
ibw.
Read transfers move data from memory to an
I 1 0 device by activating and
m.
Verify
transfers are pseudo transfers. The 8237A operates
as in Read
o r
Write transfers generating addresses,
and responding to EOP, etc. However, the memory
and I10 control lines all remain inactive. The ready
input is ignored in verify mode.
Memory-to-Memory-To perform block moves of
data from one memory address space to another
with
a minimum of program effort and time, the
8237A includes a memory-to-memory transfer fea-
ture. Programming a bit in the Command register
selects channels 0 and 1 to operate as memory-to-
memory transfer channels. The transfer is initiated
by setting the software DREQ for channel 0. The
8237A requests a DMA sew'ce in the normal man-
ner.
After HLDA is true, the device, using four state
transfers in Block Transfer mode, reads data from
the memory. The channel 0 Current Address register
is the source for the address used and is decrement-
ed or incremented in the normal manner. The data
byte read from the memory is stored in the 8237A
internal Temporary register. Channel
1
then per-
forms a four-state transfer of the data from the Tem-
porary register to memory using the address in its
Current Address register and incrementing or decre-
menting it in the normal manner. The channel 1 cur-
rent Word Count is decremented. When the word
count of channel 1 goes to FFFFH, a TC is generat-
ed causing an
Channel 0 may be programmed to retain the same
address for all transfers. This allows a single word to
be
written to a block of memory.
output terminating the service.
The 8237A will respond to external signals dur-
ing memory-to-memory transfers. Data comparators
in block search schemes may use this input to termi-
nate the service when a match is found. The timing
of memory-to-memory transfers is found in Figure
12. Memory-to-memory operations can be detected
as an active AEN with no DACK outputs.
Autolnttlallm-By programming a bit in the Mode
register, a channel may be set up as an Autoinitialize
channel. During Autoinitialize initialization, the origi-
nal values of the Current Address and Current Word
Count registers are automatically restored from the
Base Address and Base Word count registers of that
channel following
m.
The base registers are load-
ed simultaneously with the current registers by the
microprocessor and remain unchanged throughout
the DMA sew'ce. The mask bit is not altered when
the channel is in Autoinitialize. Following Autoinitial-
ize the channel is ready to perform another DMA
service, without CPU intervention, as soon as a valid
DREQ is detected. In order to Autoinitialize both
channels in a memory-to-memory transfer, both
word counts should be rogrammed identically. If in-
terrupted externally,
&
pulses should be applied
in both bus cycles.
Prlorlty-The
8237A has two types of priority en-
coding available as software selectable options. The
first is Fixed Priority which fixes the channels in pri-
ority order based upon the descending value of their
number. The channel with the lowest priority is 3
followed by 2,
1
and the highest priority channel, 0.
After the recognition of any one channel for service,
the other channels are prevented from interfering
with that sew'ce until it is completed.
After completion of a service, HRQ will go inactive
and the 8237A will wait for HLDA to go low before
activating HRQ to service another channel.
The second scheme is Rotating Priority. The last
channel to get sew'ce becomes the lowest priority
channel with the others rotating accordingly.
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