Tandy 1000 SL Technical Reference Manual page 118

With Rotating Priority in a single chip DMA system,
any device requesting service is guaranteed to be
recognized after no more than three higher priority
services have occurred. This prevents any one
channel from monopolizing the system.
Compressed liming-In order to achieve even
greater throughput where system characteristics
permit, the 8237A can compress the transfer time to
two clock cycles. From Figure 11 it can be seen that
state S3 is used to extend the access time of the
read pulse. By removing state S3, the read pulse
width is made equal to the write pulse width and a
transfer consists only of state S2 to change the ad-
dress and state S4 to perform the read/write. S1
states will still occur when A8-Al5 need updating
(see Address Generation). Timing for compressed
transfers is found in Figure 14.
Address Generation-In order to reduce pin count,
the 8237A multiplexes the eight higher order ad-
dress bits on the data lines. State S1 is used to out-
put the higher order address bits to an external latch
from which they may be placed on the address bus.
The falling edge of Address Strobe (ADSTB) is used
to load these bits from the data lines to the latch.
Address Enable (AEN) is used to enable the bits
onto the address bus through a three-state enable.
The lower order address bits are output by the
8237A directly. Lines AO-A7 should be connected
to the address bus. Figure 11 shows the time rela-
tionships between CLK, AEN, ADSTB, DBO-DB7
and AO-A7.
During Block and Demand Transfer mode services,
which include multiple transfers, the addresses gen-
erated will be sequential. For many transfers the
data held in the external address latch will remain
the same. This data need only change when a carry
or borrow from A7 to A8 takes place in the normal
sequence of addresses. To save time and speed
transfers, the 8237A executes S1 states only when
updating of A8-Al5 in the latch is necessary. This
means for long services, S1 states and Address
Strobes may occur only once every 256 transfers, a
savings of 255 cbck cycles for each 256 transfers.
REGISTER DESCRIPTION
Current Address Register-Each channel has a
16-bit Current Address register. This register holds
the value of the address used during DMA transfers.
The address is automatically incremented or decre-
mented after each transfer and the intermediate val-
ues of the address are stored in the Current Address
register during the transfer. This register is written or
read by the microprocessor in successive &bit
bytes. It may also be reinitialized by an Autoinitialize
back to its ori inal value. Autoinitialize takes place
only after an
&.
Current Word Reglster-Each channel has a 16-
bit Current Word Count register. This register deter-
mines the number of transfers to be performed. The
actual number of transfers will be one more than the
number programmed in the Current Word Count reg-
ister (i.e., programming a count of 100 will result in
101 transfers). The word count is decremented after
each transfer. The intermediate value of the word
count is stored in the register during the transfer.
When the value in the register goes from zero to
FFFFH, a TC will be generated. This register is load-
ed or read in successive &bit bytes by the micro-
processor in the Program Condition. Following the
end of a DMA service it may also be reinitialized by
an Autoinitialization back to its ori inal value. Auto-
initialize can occur only when an
&
occurs. if it is
not Autoinitialized, this register will have a count of
FFFFH after TC.
Base Address and Base Word Count Registers-
Each channel has a pair of Base Address and Base
Word Count registers. These 16-bit registers store
the original value of their associated current regis-
ters. During Autoinitialize these values are used to
restore the current registers to their original values.
The base registers are written simultaneously with
their corresponding current register in 8-bit bytes in
the Program Condition by the microprocessor.
These registers cannot be read by the microproces-
sor.
Command Reglster-This &bit register controls
the operation of the 8237A.
It
is programmed by the
microprocessor in the Program Condition and is
cleared by Reset or a Master Clear instruction. The
following table lists the function of the command
bits. See Figure 6 for address coding.
Mode Reglster-Each channel has a 6-bit Mode
register associated with it. When the register is being
written to by the microprocessor in the Program
Condition, bits 0 and 1 determine which channel
Mode register is to be written.
Request Register-The 8237A can respond to re-
quests for DMA service which are initiated by soft-
ware as well as by a DREQ. Each channel has a
request bit associated with it in the 4-bit Request
register. These are non-maskable and subject to pri-
oritization by the Priority Encoder network. Each reg-
ister bit is set or reset separately under software
control or is cleared upon generation of a TC or ex-
ternal
=.
The entire register is cleared by a Reset.
To set or reset a bit, the software loads the proper
form of the data word. See Figure
5
for register ad-
dress coding. In order to make a software request,
the channel must be in Block Mode.
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