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8237A
FUNCTIONAL DESCRIPTION
The 8237A block diagram includes the major logic
blocks and all of the internal registers. The data in-
terconnection paths are also shown. Not shown are
the various control signals between the blocks. The
8237A contains 344 bits of internal memory in the
form of registers. Figure 3 lists these registers by
name and shows the size of each. A detailed d e
scription of the registers and their functions can be
found under Register Description.
18 bb
18 bit0
18 bb
18
bb
18 bb
1 8 b b
8 b b
8 b b
8bito
6 b b
4 m
4 m
Nunkr
4
4
4
4
1
1
1
1
1
4
1
1
Flgure
3.8237A
Internal
Regl8tOr8
The 8237A contains three basic blocks of control
logic. The Timing Control block generates internal
timing and external control signals for the 8237A.
The Program Command Control block decodes the
various commands given to the 8237A by the micro-
processor prior to servicing a DMA Request. It also
decodes the Mode Control word used to select the
type
of DMA during the servicing. The Priority En-
d e r block resolves priority contention between
)MA channels requesting service simultaneously.
The Timing Control block derives internal timing
from the clock input. In 8237A systems, this input
will usually be the 42 l T L clock from an 8224 or
CLK from an 8085AH or 8284A. 33% duty cycle
clock generators, however, may not meet the dock
high time requirement of the 8237A of the same fre-
quency. For example, 82C84A-5 CLK output violates
the clock high time requirement of 8237A-5. In this
case 82C84A CLK can simply be inverted to meet
8237A-5 clock high and low time requirements. For
8085AH-2 systems above 3.9 MHz, the 8085
CLK(0UT) does not satisfy 8237A-5 clock LOW and
HIGH time requirements. In this case, an external
clock should be usod to drive the 8237A-5.
DMA OPERATION
The 8237A is designed to operate in two major
cy-
cles. These are called Idle and Active cycles. Each
device cycle is made up of a number of states. The
8237A can assume seven separate states, each
composed of one full clock period. State I (SI) is the
inactive state. It is entered when the 8237A has no
valid DMA requests pending. While in SI, the DMA
controller is inactive but may be in the Program Con-
dition, being programmed by the processor. State
S O (SO) is the first state of a DMA service. The
8237A has requested a hold but the processor has
not yet returned an acknowledge. The 8237A may
still be programmed until it receives HLDA from the
CPU. An acknowledge from the CPU will signal that
DMA transfers may begin. Si, S2,
S3
and S4 are the
working states of the DMA service. If more time is
needed to complete a transfer than is available with
normal timing, wait states (SW) can be inserted be-
tween S2 or S3 and S4 by the use of the Ready line
on the 8237A. Note that the data is transferred di-
rectl from the I 1 0 device to memory or vice versa)
with
' f aR
and
MEMW
(or
and
k)
being ac-
tive at the same time. The data is not read into or
driven out of the 8237A in 110-to-memory or memo-
ry-to-l/O DMA transfers.
Memory-to-memory transfers require a read-from
and a write-to-memory to complete each transfer.
The states, which resemble the normal working
states, use two digit numbers for identification. Eight
states are required for a single transfer. The first four
states (Sll, S12, S13, S14) are used for the read-
from-memory half and the last four states (S21, S22,
S23, S24) for the write-to-memory half of the trans-
fer.
IDLE CYCLE
When no channel is requesting service, the 8237A
will enter the Idle cycle and perform "SI" states. In
this cycle the 8237A will sample the DREQ lines ev-
ery clock cycle to determine if any channel is re-
uesting a DMA service. The device will also sample
35
looking for an attempt by the microprocessor to
write or read the internal registers of the 8237A.
When
is low and HLDA is low, the 8237A enters
the Program Condition. The CPU can now establish,
change or inspect the internal definition of the part
by reading from or writing to the internal registers.
Address lines AO-A3 are inputs to the device and
select which registers will be read or written. The
T6R
and
lines are used to select and time reads
or writes. Due to the number and size of the internal
registers, an internal flip-flop is used to generate an
additional bit of address. This bit is used to deter-
mine the upper or lower byte of the 16-bit Address
and Word Count registers. The flip-flop is reset by
Master Clear or Reset. A separate software com-
mand can also reset this flip-flop.
Special software commands can be executed by the
8237A in the Program Condition. These commands
are decoded as sets of addresses with the
and
m.
The commands do not make use of the data
bus. Instructions include Clear First/Last Flip-Flop
and Master Clear.
2-237
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