Tandy 1000 SL Technical Reference Manual page 192

NEC
Table 4. instruction Set (Notes 1,2)(cont)
I n - W
Renmrka
-
Phn4
RIW D, De
D6
DI
Da Dp DI Do
Swk
Command
W 0 0 0
0
1 1 1 1
Commandcodes
W X X X X X HD
US1
US0
w -
NCN
Execution
lnvalld
Resuil
R - SI0
-
STO=80H
Head is positioned
over
proper cylinder on diskette
Command W Invalid Codes Invalid Command codes (No op- FDC goes into standby state)
Note:
(1) SymbOls used in this table are described at the end of this section.
(2)
n,
should equal 1 for all operations.
(3) X = Don't care, usually made to equal 0.
System Configuration
Figure 2 shows an example of a system using a
pPD765AlpPD7265.
Figure 2. System Configuration
/_I
Processor Interface
During command or result phases the main status reg
ister (described earlier) must be read by the processor
before each byte of information is written into or read
from the data register. After each byte of data read or
written to the data register, CPU should wait forl2ps b e
fore reading main status register, bits D6 and @ in the
main status register must be in a 0 and 1 state, respec-
tively, before each byte of the command word may be
written into the pPD765AlpPD7265. Many of the com-
mands require multiple bytes and, as a result, the main
status register must be read prior to each byte transfer
to thepPD765AlpPD7265. On the other hand, during the
result phase, 06 and D7 in the main status register must
both be 1's
(06
=
1 and D7
=
1) before reading each byte
from thedata register. Note that this reading of the main
status register before each byte transfer to the
pPD765AlpPD7265 is required only in the command and
result phases, and not during the execution phase.
During the execution phase, the main status register
need not be read. If the pPD765AIpPD7265 is in the non-
DMA mode, then the receipt of each data byte (If
pPD765AlpPD7265 is reading data from FDD) is indi-
cated by an interrupt signal on pin 18 (INT
=
1). The gen-
eration of a read signal
(m=
0) or write signal (WR = 0)
will clear the interrupt as well as output the data onto
the data bus. If the processor cannot handle interrupts
fast enough (every 13ps for the MFM mode and 27ps for
the FM mode), then it may poll the main status register
and bit 07 (RQM) functions as the lnterru t signal. If a
write command is in process then the
&
signal ne-
gates the reset to the interrupt signal.
Note that in the non-DMA mode it is necessary to exam-
ine the main status register to determine the cause of
the interrupt, since it could be a data interrupt or a com-
mand termination interrupt, either normal or abnormal.
If the pPD765AIpPD7265 is in the DMA mode, no inter-
rupts are generated during the execution phase. The
pPD765AIpPD7265 generates DRQs (DMA requests)
when each byte of data is available. T K M A controller
responds to this request with both a DACK
=
0 (DMA ac-
knowledge) and an RD
=
0 (read signal). When the DMA
acknowledge signal goes low (DXK=O), then the DMA
request is cleared (DRQ
= 0).
If a write command has
been issued then a m s i g n a l will appear instead of
m.
After the execution phase has been completed (terminal
count has occurred) or the EOT sector readlwrltten,
then an interrupt will occur (INT= 1). Thls signifies the
beginning of the result phase. When the first byte of
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