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PROGRAMMING
The 8237A will accept programming from the host
processor any time that HLDA is inactive; this is true
even
if
HRQ is active. The responsibility of the host
is to assure that programming and HLDA are mutual-
ly exclusive. Note that a problem can occur if a DMA
request occurs, on an unmasked channel while the
8237A is being programmed. For instance, the CPU
may be starting to reprogram the two byte Address
register of channel 1 when channel
1
receives a
DMA request. If the 8237A is enabled (bit 2 in the
command register is 0) and channel 1
is
unmasked,
a DMA service will occur after only one byte of the
Address register has been reprogrammed. This can
be avoided by disabling the controller (setting bit 2 in
the command register) or masking the channel be-
fore programming any other registers. Once the pro-
gramming is complete, the controller can be en-
abledhnmasked.
After power-up it is suggested that all internal loca-
tions, especially the Mode registers, be loaded with
some valid value. This should be done even if some
channels are unused. An invalid mode may force all
control signals to go active at the same time.
APPLICATION INFORMATION (Note 1)
Figure 8 shows a convenient method for configuring
a DMA system with the 8237A controller and an
8080A/8085AH microprocessor system. The multi-
mode DMA controller issues a HRQ to the processor
whenever there is at least one valid DMA request
from a peripheral device. When the processor re-
plies with a HLDA signal, the 8237A takes control of
the address bus, the data bus and the control bus.
The address for the first transfer operation comes
out in two bytes-the least significant 8 bits on the
eight address outputs and the most significant 8 bits
on the data bus. The contents of the data bus are
then latched into an 8-bit latch to complete the full
16 bits
of the address bus. The 8282 is a high
speed, &bit, three-state latch in a 20-pin package.
After the initial transfer takes place, the latch is up-
dated only after a carry or borrow is generated in the
least significant address byte. Four DMA channels
are provided when one 8237A is used.
CCU
SVSTEY
DATA I U S
J
231466-1 1
Figure 8.8237A System Interface
NOTE:
1.
See Application Note AP-67 for 8086 design information.
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