Dram Control; Refresh Control - Tandy 1000 SL Technical Reference Manual

DRAM
C o n t r o l
The CPU a d d r e s s d e c o d e f o r t h e Dynamic Random
Access Memory
(DRAM)
a r r a y
i s
g e n e r a t e d by t h e 8079024 c u s t o m ( U 4 1 ) . T h e s e
s i g n a l s
are
l a t c h e d b y ALE i n t e r n a l l y
t o
t h e 8079024 c u s t o m I C
a n d h e l d f o r t h e c o m p l e t e c y c l e . The a d d r e s s d e c o d e s i g n a l s
are
RASO-, RAS1-, RAS2-, RAS3-, a n d CAS-. Memory c o n f i g u r a t i o n s
s u p p o r t e d by t h e Tandy 1 0 0 0 SL
a r e
256K, 512K,
o r
640K b y t e s ( i n
a d d i t i o n
t o
128K
of
v i d e o memory). The f o l l o w i n g t a b l e shows t h e
d i f f e r e n t o p t i o n s a v a i l a b l e o n t h e 8079024 c u s t o m I C .
Memory MCONFIGl MCONFIGO S y s t e m T o t a l S y s t e m
O p t i o n Memory Memory
*
0
0 0
1 0 1
2
1
0
3 1 1
256K
512K
512K
640K
384K
64
OK
640K
768K
*
Note: T o t a l s y s t e m memory i n c l u d e s 128K of v i d e o memory.
Memory O p t i o n 0
i s t h e power u p d e f a u l t .
Memory c o n f i g u r a t i o n s .
The s i g n a l s WEL- a n d WEH- p r o v i d e
w r i t e
c o n t r o l . F o r
a
1 6 - b i t
access,
b o t h
are
a s s e r t e d
a t
t h e
same t i m e
a n d
are
c o n t r o l l e d by
MEMW-
(memory
w r i t e ) .
F o r a n 8 - b i t
access,
t h e a p p r o p r i a t e s i g n a l
i s asserted a c c o r d i n g t o t h e s t a t e o f A0 ( h i g h b y t e o r l o w
b y t e ) .
R e f r e s h C o n t r o l
R e f r e s h t i m i n g is d e r i v e d i n t e r n a l
t o
t h e 8079024 c u s t o m
I C
(U41)
a n d p r o v i d e s
a
5 1 2 c o u n t , 8
msec, RAS o n l y r e f r e s h f o r i n t e r n a l
memory, a n d a 256 c o u n t , 4
msec, RAS o n l y r e f r e s h f o r t h e b u s .
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