Memory (Ram); Dram Block Diagram - Tandy 26-3334 Service Manual

5.2 Memory
(RAM)
The Color Computer
3
uses Dynamic
Random Access Memories {DRAMs
-
IC16
through IC19). Each memory chip
is
capable
of
storing 262,144 bits (64K
x
4)
,
any one of which
may be
accessed
at any given
time. Since
the
CPU needs
to
access eight data bits
at
a
time, two DRAMs are used.
Therefore,
the
memory array
is said
to be 64K
x
8.
The dual Write Enable
signals (WEO*, WEI*)
to the
DRAM
control
2
banks of 64K
x
8
memory
(total of 128K
x 8). The DRAMs
in the
Color Computer
3
operate off
of
a
single
+5 volt supply.
In order
to
address
a
64K location
in
each chip,
16
address lines are
required. However, since
the DRAM
package
has only
18
pins, the
addresses
are multiplexed
into two
groups
of
8
and
8,
called row address
and column address.
(See Figure
5-4.)
The row address
is
presented
first,
and the DRAM
is informed that this
is
the row address by
the presence
of
RAS* (row address strobe) and
the
absence
of
CAS* (column address
strobe). After
the DRAM
has latched
the least significant eight addresses
(the row addresses), the column
addresses
are presented, along
with
CAS*.
If the present cycle
is a
read
cycle, WE* (Write Enable)
is
held
high, and
the
data
is
retrieved from
the
appropriate cell and presented
at
the output pin some
time later.
The
actual
time depends on
the access
time of the DRAM.
During
a
write
cycle, the data and
WE*
signal are
active prior
to
CAS* and are latched
in
at
CAS*
time. Figure
5-5 shows the
read and
write timing cycles
for
DRAM.
Dynamic memory
is
called dynamic
because
it
requires refreshing
at
periodic intervals
in order
to
remember. Refresh
is
accomplished
by
providing
the
DRAMs with RAS* signal
and an address count. The address
count must toggle through
all 256 row
address possibilities
in 4
milli-
seconds
or less.
(If you don't remind
the
DRAM
of what
it
knew
at
least
once every
4
milliseconds,
it will
forget.
CLOCK
GEN
NO.
I
CAS
REF
CONTROL
CLOCK
I
INTERNAL
ADDRESS
COUNTER
Vtt
Ao
'
Ai
—
A2
—
Aj-
A4
—
A3
—
UJ
tu
a
ra
<t
m
A6
—
At
—
AO-A7
rTCH
CLOCK GEN
NO.
COLUMN
DECODER
SENSE
AMPS
I/O
GATING
a:
W Q
O
O
UJ
a
o
WRITE
CLOCK
GEN.
262,144
BIT
STORAGE
CELL
X
DATA
IN
BUFF.
DATA
OUT
BUFF,
-WE
-DQI^DQ4
OE
~a
Vcc
-
—
Vss
Figure
5-4.
DRAM Block Diagram
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