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INTERRUPT STRUCTURE
PERIPHERAL INTERRUPT CONTROL REGISTERS
For each interrupt source there is one or more corresponding peripheral control registers that let you control the
interrupt generated by the related peripheral (see Table 5-3).
Interrupt Source
Timer A overflow
Timer A match/capture
Timer B match
Timer 0 match
Timer 1 overflow
Timer 1 match/capture
SIO interrupt
Watch timer overflow
P0.3 external interrupt
P0.2 external interrupt
P0.1 external interrupt
P0.0 external interrupt
P0.7 external interrupt
P0.6 external interrupt
P0.5 external interrupt
P0.4 external interrupt
NOTE: Because the timer 0 overflow interrupt is cleared by hardware, the T0CON register controls only the enable/disable
functions. The T0CON register contains enable/disable and pending bits for the timer 0 match/capture interrupt.
5-8
Table 5-3. Interrupt Source Control and Data Registers
Interrupt Level
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
S3C8248/C8245/P8245/C8247/C8249/P8249
Register(s)
TACON
TACINT
TADATA
TBCON
TBDATAH, TBDATAL
T0CON, T0CNTH
T0CNTL, T0DATAH
T0DATAL
T1CON
T1CNTH
T1CNTL
T1DATAH
T1DATAL
SIOCON
SIODATA
SIOPS
WTCON
P0CONL
P0INT
P0PND
P0CONH
P0INT
P0PND
Location(s) in Set 1
EDH, bank 0
EEH, bank 0
EFH, bank 0
ECH, bank 0
EAH, EBH, bank 0
F1H, F2H, bank 1
F3H, F4H, bank 1
F5H, bank 1
FBH, bank 1
FCH, bank 1
FDH, bank 1
FEH, bank 1
FFH, bank 1
F0H, bank 0
F1H, bank 0
F2H, bank 0
FAH, bank 1
E1H, bank 0
E2H, bank 0
E3H, bank 0
E0H, bank 0
E2H, bank 0
E3H, bank 0
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