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S3C8248/C8245/P8245/C8247/C8249/P8249
INTERRUPT PROCESSING CONTROL POINTS
Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source.
The system-level control points in the interrupt structure are:
— Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0 )
— Interrupt level enable/disable settings (IMR register)
— Interrupt level priority settings (IPR register)
— Interrupt source enable/disable settings in the corresponding peripheral control registers
When writing an application program that handles interrupt processing, be sure to include the necessary
register file address (register pointer) information.
EI
RESET
IRQ0-IRQ7,
Interrupts
S
Q
R
Interrupt Priority
Register
Figure 5-4. Interrupt Function Diagram
NOTE
Interrupt Request Register
(Read-only)
Interrupt Mask
Register
Global Interrupt Control
INTERRUPT STRUCTURE
Polling
Cycle
(EI, DI or SYM.0
manipulation)
Vector
Interrupt
Cycle
5-7
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