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S3C8248/C8245/P8245/C8247/C8249/P8249
Vector Address
Decimal
Value
Value
256
100H
226
224
228
230
234
232
236
238
246
244
242
240
254
252
250
248
NOTES:
1.
Interrupt priorities are identified in inverse order: "0" is the highest priority, "1" is the next highest, and so on.
2.
If two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority
over one with a higher vector address. The priorities within a given level are fixed in hardware.
3.
Timer A or Timer 1 can not service two interrupt sources simultaneously, then only one interrupt source have to be used.
Table 5-1. Interrupt Vectors
Interrupt Source
Hex
Basic timer overflow
E2H
Timer A overflow
E0H
Timer A match/capture
E4H
Timer B match
E6H
Timer 0 match
EAH
Timer 1 overflow
E8H
Timer 1 match/capture
ECH
SIO interrupt
EEH
Watch timer overflow
F6H
P0.3 external interrupt
F4H
P0.2 external interrupt
F2H
P0.1 external interrupt
F0H
P0.0 external interrupt
FEH
P0.7 external interrupt
FCH
P0.6 external interrupt
FAH
P0.5 external interrupt
F8H
P0.4 external interrupt
INTERRUPT STRUCTURE
Request
Interrupt
Priority in
Level
Level
RESET
–
IRQ0
1
0
IRQ1
–
IRQ2
–
IRQ3
1
0
IRQ4
–
IRQ5
–
IRQ6
3
2
1
0
IRQ7
3
2
1
0
Reset/Clear
H/W
S/W
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
5-5
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