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S3C8248/C8245/P8245/C8247/C8249/P8249
Port 5 Control Register, Low Byte
EFH, Set 1, Bank 1, R/W
MSB
.7
.6
.5
P5.2/SEG26
P5.3/SEG27
P5CONL bit-pair pin configuration settings
00
Input mode
01
Input mode, pull-up
10
Opendrain output mode
11
Output mode, push-pull
NOTE: If LCD is enabled by LCON.6, SEG signal go out
otherwise port 5 I/0 can be selected.
Figure 9-15. Port 5 Low-Byte Control Register (P5CONL)
.4
.3
.2
.1
P5.0/SEG24
P5.1/SEG25
.0
LSB
I/O PORTS
9-15
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