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S3C8248/C8245/P8245/C8247/C8249/P8249
BLOCK DIAGRAM
Bits 7, 6, 5
TBOF
fxx/256
fxx/64
fxx/8
fxx/1
NOTES:
1.
To be loaded T0DATA value to buffer register for comparing, T0CON.3 bit must be set 1.
2.
Timer 0 input clock must be slower than CPU clock.
M
16-bit up-Counter H/L
U
X
Bit 2
Timer 0 Data H/L Reg
Figure 12-2. Timer 0 Functional Block Diagram
Data Bus
8
R
(Read Only)
16-bit Comparator
Timer 0 Buffer Reg
(Read/Write)
8
Data Bus
Bit 3
Clear
Pending
Bit 0
Match
Bit 1
Counter clear signal (T0CON.3)
16-BIT TIMER 0/1
T0INT
IRQ2
12-3
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