Samsung S3C8248 User Manual page 209

I/O PORTS
9-4
Port 0 Control Register, High Byte (P0CONH)
E0H, Set 1, Bank 0, R/W
MSB .7 .6 .5
P0.7 P0.6
(INT7) (INT6)
P0CONH bit-pair pin configuration
00 Schmitt trigger input mode, pull-up, interrupt on falling edge
01 Schmitt trigger input mode, interrupt on rising edge
10 Schmitt trigger input mode, interrupt on rising or falling edge
11 Output mode, push-pull
Figure 9-1. Port 0 High-Byte Control Register (P0CONH)
Port 0 Control Register, Low Byte (P0CONL)
E1H, Set 1, Bank 0, R/W
MSB .7 .6 .5
P0.3 P0.2
(INT3) (INT2)
P0CONL bit-pair pin configuration
00 Schmitt trigger input mode, pull-up, interrupt on falling edge
01 Schmitt trigger input mode, interrupt on rising edge
10 Schmitt trigger input mode, interrupt on rising or falling edge
11 Output mode, push-pull
Figure 9-2. Port 0 Low-Byte Control Register (P0CONL)
S3C8248/C8245/P8245/C8247/C8249/P8249
.4 .3 .2 .1
P0.5 P0.4
(INT5) (INT4)
.4 .3 .2 .1
P0.1 P0.0
(INT1) (INT0)
.0 LSB
.0 LSB