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S3C8248/C8245/P8245/C8247/C8249/P8249
A/D CONVERTER
15
10-BIT ANALOG-TO-DIGITAL CONVERTER
OVERVIEW
The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at
one of the eight input channels to equivalent 10-bit digital values. The analog input level must lie between the
AV
and AV
values. The A/D converter has the following components:
REF
SS
— Analog comparator with successive approximation logic
— D/A converter logic (resistor string type)
— ADC control register (ADCON)
— Eight multiplexed analog data input pins (ADC0–ADC7)
— 10-bit A/D conversion data output register (ADDATAH/L)
— 10-bit digital input port (Alternately, I/O port.)
— AV
and AV
pins, AV
is internally connected to V
REF
SS
SS
SS
FUNCTION DESCRIPTION
To initiate an analog-to-digital conversion procedure, at the first you must set ADCEN signal for ADC input
enable at port 2, the pin set with 1 can be used for ADC analog input. And you write the channel selection data in
the A/D converter control register ADCON.4–.7 to select one of the eight analog input pins (ADC0–7) and set the
conversion start or enable bit, ADCON.0. The read-write ADCON register is located in set 1, bank 0, at address
F3H. The pins witch are not used for ADC can be used for normal I/O.
During a normal conversion, ADC logic initially sets the successive approximation register to 200H (the
approximate half-way point of an 10-bit register). This register is then updated automatically during each
conversion step. The successive approximation block performs 10-bit conversions for one input channel at a
time. You can dynamically select different channels by manipulating the channel selection bit value (ADCON.6–
4) in the ADCON register. To start the A/D conversion, you should set the enable bit, ADCON.0. When a
conversion is completed, ADCON.3, the end-of-conversion(EOC) bit is automatically set to 1 and the result is
dumped into the ADDATAH/L register where it can be read. The A/D converter then enters an idle state.
Remember to read the contents of ADDATAH/L before another conversion starts. Otherwise, the previous result
will be overwritten by the next conversion result.
NOTE
Because the A/D converter has no sample-and-hold circuitry, it is very important that fluctuation in the analog
level at the ADC0–ADC7 input pins during a conversion procedure be kept to an absolute minimum. Any change
in the input level, perhaps due to noise, will invalidate the result. If the chip enters to STOP or IDLE mode in
conversion process, there will be a leakage current path in A/D block. You must use STOP or IDLE mode after
ADC operation is finished.
15-1
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