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Samsung S3C8248 User Manual page 127

8-bit cmos

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INSTRUCTION SET
BITR
— Bit Reset
BITR
dst.b
dst(b) ← 0
Operation:
The BITR instruction clears the specified bit within the destination without affecting any other bits
in the destination.
Flags:
No flags are affected.
Format:
opc
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'
Example:
Given: R1 = 07H:
BITR
If the value of working register R1 is 07H (00000111B), the statement "BITR R1.1" clears bit one
of the destination register R1, leaving the value 05H (00000101B).
6-20
dst | b | 0
is three bits, and the LSB address value is one bit in length.
R1.1
R1 = 05H
S3C8248/C8245/P8245/C8247/C8249/P8249
Bytes
Cycles
Opcode
2
4
Addr Mode
(Hex)
dst
77
rb

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