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S3C8248/C8245/P8245/C8247/C8249/P8249
S3C8248/C8245/C8247/C8249 INTERRUPT STRUCTURE
The S3C8248/C8245/C8247/C8249 microcontroller supports sixteen interrupt sources. All sixteen of the interrupt
sources have a corresponding interrupt vector address. Eight interrupt levels are recognized by the CPU in this
device-specific interrupt structure, as shown in Figure 5-2.
When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which
contending interrupts are to be serviced. If multiple interrupts occur within the same interrupt level, the interrupt
with the lowest vector address is usually processed first (The relative priorities of multiple interrupts within a
single level are fixed in hardware).
When the CPU grants an interrupt request, interrupt processing starts. All other interrupts are disabled and the
program counter value and status flags are pushed to stack. The starting address of the service routine is fetched
from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the
service routine is executed.
Levels
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
NOTES:
1. Within a given interrupt level, the low vector address has high priority.
For example, E0H has higher priority than E2H within the level IRQ.0 the priorities within each
level are set at the factory.
2. External interrupts are triggered by a rising or falling edge, depending on the corresponding control
register setting.
Vectors
E0H
E2H
E4H
E6H
E8H
EAH
ECH
EEH
F0H
F2H
F4H
F6H
F8H
FAH
FCH
FEH
Figure 5-2. S3C8248/C8245/C8247/C8249 Interrupt Structure
Sources
Timer A match/capture
Timer A overflow
Timer B match
Timer 0 match
Timer 1 match/capture
Timer 1 overflow
SIO interrupt
Watch timer overflow
P0.0 external interrupt
P0.1 external interrupt
P0.2 external interrupt
P0.3 external interrupt
P0.4 external interrupt
P0.5 external interrupt
P0.6 external interrupt
P0.7 external interrupt
INTERRUPT STRUCTURE
Reset/Clear
H/W,S/W
H/W,S/W
H/W
H/W,S/W
H/W,S/W
H/W,S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
5-3
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