Flash Status Register (Flash_Sr) - ST STM32F101xx series Programming Manual

PM0075
3.4

Flash status register (FLASH_SR)

Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29
15 14 13
Bits 31:6 Reserved, must be kept cleared.
Bit 5 EOP: End of operation
Note: EOP is asserted at the end of each successful program or erase operation
Bit 4 WRPRTERR: Write protection error
Bit 3 Reserved, must be kept cleared.
Bit 2 PGERR: Programming error
Note: The STRT bit in the FLASH_CR register should be reset before starting a programming
Bit 1 Reserved, must be kept cleared
Bit 0 BSY: Busy
28 27 26 25
12 11 10 9
Reserved
Set by hardware when a Flash operation (programming / erase) is completed. Reset by
writing a 1
Set by hardware when programming a write-protected address of the Flash memory.
Reset by writing 1.
Set by hardware when an address to be programmed contains a value different from
'0xFFFF' before programming.
Reset by writing 1.
operation.
This indicates that a Flash operation is in progress. This is set on the beginning of a Flash
operation and reset when the operation finishes or when an error occurs.
24 23 22
Reserved
8 7 6
Doc ID 17863 Rev 1
Register descriptions
21 20 19 18
5 4 3 2
WRPRT PG
EOP
ERR ERR
Res.
rw rw rw
17 16
1 0
BSY
Res.
r
25/31