DIGITAL-LOGIC Microspace MSM586SEN Technical User Manual page 140

DIGITAL-LOGIC AG MSM586SEN/SEV Manual V1.5E
SAO-SA19, LA17 - LA23 input/output
Address bits 0 through 19 are used to address memory and I/0 devices within the system. These 20 address
lines, allow access of up to 1MBytes of memory. SAO through SA19 are gated on the system bus when
BALE is high and are latched on the falling edge of BALE. LA17 to LA23 are not latched and addresses the
full 16 MBytes range. These signals are generated by the microprocessors or DMA controllers. They may
also be driven by other microprocessor or DMA controllers that reside on the I/0 channel. The SA17-SA23
are always LA17-LA23 address timings for use with the MSCS16 signal. This is advanced AT96 design. The
timing is selectable with jumpers LAxx or SAxx.
/SBHE, input/output
Bus High Enable (system) indicates a transfer of data on the upper byte of the data bus, XD8 through XD15.
Sixteen-Bit devices use /SBHE to condition data-bus buffers tied to XD8 through XD15.
SD[O..15], input/output
These signals provide bus bits 0 through 15 for the microprocessor, memory, and I/0 devices. DO is the
least-significant Bit and D15 is the most significant Bit. All 8-Bit devices on the I/O channel should use DO
through D7 for communications to the microprocessor. The 16-Bit devices will use DO through D15. To sup-
port 8-Bit device, the data on D8 through D15 will be gated to DO through D7 during 8-Bit transfers to these
devices; 16-Bit microprocessor transfers to 8-Bit devices will be converted to two 8-Bit transfers.
/SMEMR input/output
These signals instruct the memory devices to drive data onto the data bus for the first MByte. /SMEMR is
active on all memory read cycles. /SMEMR may be driven by any microprocessor or DMA controller in the
system. When a microprocessor on the I/0 channel wishes to drive /SMEMR, it must have the address lines
valid on the bus for one system clock period before driving /SMEMR active. The signal is active low.
/SMEMW, input/output
These signals instruct the memory devices to store the data present on the data bus for the first MByte.
/SMEMW is active in all memory read cycles. /SMEMW may be driven by any microprocessor or DMA con-
troller in the system. When a microprocessor on the I/O channel wishes to drive /SMEMW, it must have the
address lines valid on the bus for one system clock period before driving /SMEMW active. Both signals are
active low.
SYSCLK, output
This is a 8.25 MHz system clock. It is a synchronous microprocessor cycle clock with a cycle time of 167
nanoseconds. The clock has a 66% duty cycle. This signal should only be used for synchronization.
Available on ELAN520, since boardversion V2.2
TC output
Terminal Count provides a pulse when the terminal count for any DMA channel is reached. The TC com-
pletes a DMA-Transfer. This signal is expected by the onboard floppy disk controller. Do not use this signal,
because it is internally connected to the floppy controller.
/0WS, input
The Zero Wait State (/0WS) signal tells the microprocessor that it can complete the present bus cycle without
inserting any additional wait cycles. In order to run a memory cycle to a 16-Bit device without wait cycles,
/0WS is derived from an address decode gated with a Read or Write command. In order to run a memory
cycle to an 8-Bit device with a minimum of one-wait states, /0WS should be driven active one system clock
after the Read or Write command is active, gated with the address decode for the device. Memory Read and
Write commands to an 8-Bit device are active on the falling edge of the system clock. /OWS is active low
and should be driven with an open collector or tri-state driver capable of sinking 20mA.
Not available on ELAN520
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