DIGITAL-LOGIC AG 1. P REFACE The information contained in this manual has been carefully checked and is believed to be accurate; it is subject to change without notice. Product advances mean that some specifications may have changed. DIGITAL-LOGIC AG assumes no responsibility for any inaccuracies, or the consequences thereof, that may appear in this manual.
DIGITAL-LOGIC AG 1.5. Recycling Information All components within this product fulfill the requirements of the RoHS (Restriction of Hazardous Substances Directive). The product is soldered with a lead free process. 1.6. Technical Support 1. Contact your local DIGITAL-LOGIC Technical Support, in your country. 2.
DIGITAL-LOGIC AG 1.8. Explanation of Symbols CE Conformity This symbol indicates that the product described in this manual is in compliance with all applied CE standards. Caution, Electric Shock! This symbol and title warn of hazards due to electrical shocks (> 60V) when touching products or parts of them.
DIGITAL-LOGIC AG RoHS is often referred to as the "lead-free" directive but it restricts the use of the following substances: Lead Mercury Cadmium Chromium VI PBB and PBDE The maximum allowable concentration of any of the above mentioned substances is 0.1% (except for Cadmium, which is limited to 0.01%) by weight of homogeneous material.
DIGITAL-LOGIC AG 1.12. Swiss Quality 100% Made in Switzerland DIGITAL-LOGIC is a member of "Swiss-Label" This product was not manufactured by employees earning piecework wages This product was manufactured in humane work conditions All employees who worked on this product are paid customary Swiss market wages and are insured ISO 9000:2001 (quality management system) 1.13.
DIGITAL-LOGIC AG 2. O VERVIEW 2.1. Standard Features The smartCoreExpress is an electrical and mechanical definition for a COM or Computer on Module (miniaturized PC system), based on Intel's ATOM chip unit incorporating the major elements of a PC compatible computer. Powerful though low consumption ATOM CPU Soldered DDR2 RAM 512k up to 2GByte Single 220pin connectors (Tyco) for the smartCoreExpress BUS...
DIGITAL-LOGIC AG 2.2. Technical Specifications CoreDuo / Celeron M Clock Level Cache Level Cache Technology VCCCore @ 1.6GHz VCCCore @ 1.1GHz VCCCore @ deep sleep CPU BUS AGTL+ Termination Mathematics Coprocessor Intel US15W Graphics Memory Controller Hub Memory Controller Supports Socket Technologies Capacity...
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DIGITAL-LOGIC AG Intel US15W PCIe BUS EIDE BUS SATA BUS USB V2.0 APIC Sound IRQ Controller Timers Power Management Reset & Power Management Controller Power Modes ACPI PCIexpress Power Supply DC Input Inrush Current Standby Power Onboard Voltages Power Consumption Physical Characteristics Dimensions Weight...
DIGITAL-LOGIC AG Operating Environment Relative Humidity Vibration Shock Operating Temperature Maximum Copper Temperature Storage Temperature EMI / EMC (IEC1131-2 refer MIL 461/462) ESD Electro Static Discharge REF Radiated Electromagnetic Field EFT Electric Fast Transient (Burst) SIR Surge Immunity Requirements High-Frequency Radiation All information is subject to change without notice.
DIGITAL-LOGIC AG Design IN with the smartModule Attention! When using an active/passive heatsink that is not from DLAG, be very careful! The maximum depth the screws can go into the product is 3mm or the module will be destroyed! 3.2. Dimensions of the smartCoreExpress Module 3.25 3.25 58.0...
DIGITAL-LOGIC AG 3.3. Connector Placement & Pin Definition on the Carrier Board View of the Top Side (mounting side) of the smartCoreExpress PCB: d=2.2/D=4.5 3.25 3.25 d=2.2/D=4.5 d=1.0 3.6mm A1 A2 A3 ... smartCoreExpress 44.0mm PCB pad design 58.5mm 50.2mm 57.7mm SMA200 Manual V1.0 B110...
DIGITAL-LOGIC AG 3.5. Dimensions of the Carrier Board Connector SMX-CON8: Standard Height: 5.0mm DLAG Part Nr: 807138 AMP/Tyco: 8-6318491-6 (Components placed below the smartModule should total a maximum of 2.0mm.) 3.6. Component Heights between Module and Carrier Board Parts mounted on the back side of the module (in the space between the bottom surface of the module PCB and the carrier board) should have a maximum height of 8.0mm.
DIGITAL-LOGIC AG 4. COM-E XPRESS 4.1. Signal Terminology Descriptions Signal Description Internally implemented pull up resistor Internally implemented pull down resistor I/O 3.3V Bi-directional signal 3.3V tolerant I/O 5V Bi-directional signal 5V tolerant I 3V Input 3.3V tolerant I 5V Input 5V tolerant I/O 3.3VSB Input 3.3V tolerant, active in standby state...
DIGITAL-LOGIC AG SMA200 Manual V1.0 5. S IGNAL ESCRIPTIONS OF THE SMART XPRESS 5.1. Wire Design for Typical Impedances 5.2. Matching of the Differential Pairs...
DIGITAL-LOGIC AG SMA200 Manual V1.0 5.3. Placing an AC Coupling Capacitor on each PCIe-TX In the smartCoreExpress module, all PCI-TX pairs already include the series AC capacitors.
DIGITAL-LOGIC AG 5.4. smartCoreExpress Signal Groups 5.4.1. PCI-Express Signal Type Description PCIe_Tx [0-4] +/- PCIe PCIe_Rx [0..4] +/- PCIe PCIe_CLK[0..4] +/- PCIe PCIe_REQ#[0..4] PCIe 3.3V If the signals are not used: All these PCI-Express signals may be left open. Remarks: Pair to Pair spacing: BUS to BUS spacing: The AC coupling capacitors must be placed near the device for the Tx signals only.
DIGITAL-LOGIC AG 5.4.2. SDVO Signal Type SDVO_CTRLCLK SDVO SDVO_CTRLDAT SDVO SDVO_CLK +/- SDVO SDVO_INIT +/- SDVO SDVO_STALL +/- SDVO SDVO_TVCLKIN +/- SDVO SDVO_Red +/- SDVO SDVO_Green +/- SDVO SDVO_Blue +/- SDVO If the signals are not used: All these SDVO signals may be left open. Remarks: For the DDC signals, a voltage translator to 3.3V or 5V is needed.
DIGITAL-LOGIC AG 5.4.3. LVDS Signal Type LVDS_DDCCLK LVDS 3.3V DDC signal LVDS_DDCDAT LVDS 3.3V DDC signal LVDS_DATA[0..3] +/- LVDS LVDS_CLK +/- LVDS LVDS_VDDEN LVDS 3.3V LVDS_BKLCTL LVDS 3.3V LVDS_BKLEN LVDS 3.3V LVDS_CTLA_CLK LVDS 3.3V LVDS_CTLB_DATA LVDS 3.3V If the signals are not used: All these LVDS signals may be left open.
DIGITAL-LOGIC AG 5.4.4. Signal Type Description USB_[0..7] +/- USB_OC[0..7]# 3.3V If the signals are not used: All these USB signals may be left open. Remarks: EMV/EMI-filters: Use a choke and clamping diode on each signal pair. On Module Termination Differential USB data signal pair USB overcurrent signal PU 10k to...
DIGITAL-LOGIC AG 5.4.5. Parallel ATA Signal Type Description PATA_D[15..0] CMOS PATA_A[0..2] CMOS PATA_IOR#] CMOS PATA_IOW#] CMOS PATA_DACK#] CMOS PATA_CS[3,1] CMOS PATA_REQ CMOS 3/5V PATA_IORDY CMOS PATA_IRQ CMOS PATA_PCSEL CMOS If the signals are not used: All this PATA signals may be left open. Remarks: EMV/EMI filters: Are not needed.
DIGITAL-LOGIC AG 5.4.6. LPC BUS Signal Type LPC_FRAME# CMOS 3.3V LPC_AD[3..0] CMOS 3.3V LPC_SERIRQ CMOS 3.3V LPC_CLKOUT[0..1] CMOS 3.3V If the signals are not used: Leave the pins open. Remarks: Use 33 Ohm series termination in each LPC-CLKx-signal. The LPC_CLKOUTx may drive only 2 loads. EMV/EMI filters: Are not needed.
DIGITAL-LOGIC AG 5.4.7. SMBus Signal Type SMB_ALERT# CMOS 3.3V SMB_DATA CMOS 3.3V SMB_CLOCK CMOS 3.3V If the signals are not used: The pins can stay open. Remarks: The SMB_ALERT# may be used to initiate an SMB event over APIC or an SMI. Maximum BUS capacitance is 200pF.
DIGITAL-LOGIC AG 5.4.8. HDA Audio Interface Signal Type HDA_DOCKEN# CMOS 3.3V HAD_RST# CMOS 3.3V HAD_SYNC CMOS 3.3V HAD_BITCLK CMOS 3.3V HAD_SDATAin [1..0] CMOS 3.3V HAD_SDATAout CMOS 3.3V HAD_DOCKRST# CMOS 3.3V If the signals are not used: Remarks: The 33 Ohm series termination should be placed directly next to the codecs. Supported Codecs: EMV/EMI filters: Are not needed.
DIGITAL-LOGIC AG 5.4.9. SD / SDIO Interface Signal Type SD0_CD# CMOS 3.3V SD0_CLK CMOS 3.3V SD0_CMD# CMOS 3.3V SD_Data [3..0] CMOS 3.3V SD0_LED CMOS 3.3V SD0_PWR# CMOS SD0_WP CMOS If the signals are not used: Remarks: EMV/EMI filters: Are not needed. On Module Description Termination...
DIGITAL-LOGIC AG 5.4.10. SPI BUS Signal Type Description SPI_MISO CMOS 3.3V Connect to the SPI device. SPI_MOSI CMOS 3.3V Connect to the SPI device. SPI_CLK CMOS 3.3V Connect to the SPI device. f = 17.86 and 31.25MHz SPI_CS# CMOS 3.3V Connect to the SPI device.
DIGITAL-LOGIC AG 5.4.11. SATA Interface (Option) Signal Type SATA_Tx[0..3] SATA SATA_Rx[0..3] SATA If the signals are not used: Unused SATA interfaces may be open. Remarks: The 10nF capacitors 0402 need to be placed directly at the SATA connector. Maximum via count is 2 per signal. BUS to BUS spacing is min.
DIGITAL-LOGIC AG 5.4.12. GLAN Signal Type Description GLAN_TX +/- GLAN GLAN_RX +/- GLAN GLAN-CLK +/- GLAN LCI_TXD[2..0] LCI 3.3V LCI_RXD[2..0] LCI 3.3V LCI_RST 3.3V If the signals are not used: Unused GLAN /LCI interfaces may be open. Remarks: The 10nF capacitors 0402 need to be placed directly at the SATA connector. Maximum via count is 2 per signal.
DIGITAL-LOGIC AG 5.4.13. CAN / Serial Signal Type Description CAN_TX CMOS 3.3V CAN_RX CMOS 3.3V If the signals are not used: Unused interfaces may be open. Remarks: EMV/EMI filters: Are not needed. On Module Termination Serial output. Res. Serial input. Res.
DIGITAL-LOGIC AG 5.4.15. Supply Signal Type +5Volt +5V Always VCCRTC On Module Description Termination 5V power supply input. Switched with the sus4signal 5V Always available. RTC supply 3.0-3.6Volt. Connect to a lithium battery, using a 1k series resistor. SMA200 Manual V1.0 Ext.
DIGITAL-LOGIC AG SMART The connector type is equal to the COMexpress connector. This is a 220pin, surface-mounted connector with 0.5mm pitch. Parameter Material Electrical Mechanical The manufacturer of the connector is: Source on smartCore Carrier Board Connector TYCO / AMP smartCoreExpress Module Connector TYCO / AMP The stack height may be defined on the carrier board as either 5 or 8mm using the two different connector...
DIGITAL-LOGIC AG SMART The smartCoreExpress supports small footprints and especially mobile applications. It is powered by the modern Intel Atom CPU technology. To select the correct module, this chapter compares the different PCIe-based module concepts. All concepts allow minimum (required) and maximum (optional) features. The following table summarizes the features of all PCIe COMs.
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