Panasonic FP0R User Manual page 181

Cancelling high-speed counter instructions (bit 3)
Enabling/disabling the reset input (hardware reset) of the high-speed counter (bit 2)
FP0R User's Manual
Operations performed by the high-speed counter control code:
 Cancelling high-speed counter instructions (bit 3)
Enabling/disabling the reset input (hardware reset) of the high-speed

counter (bit 2)
Enabling/disabling counting operations (bit 1)

Resetting the elapsed value (software reset) of the high-speed counter

to 0 (bit 0)
To cancel execution of an instruction, set bit 3 of the data register storing
the high-speed counter control code (sys_wHscOrPulseControlCode) to
TRUE. The high-speed counter control flag then changes to FALSE. To
re-enable execution of the high-speed counter instruction, reset bit 3 to
FALSE.
X0 High-speed counter input
Q Elapsed value
W Bit 2 of high-speed counter control code (enable/disable reset input)
E Elapsed value is reset to 0
R Reset not possible
When bit 2 of the control code is set to TRUE, a hardware reset using the
reset input specified in the system registers is not possible. Counting will
continue even if the reset input has turned to TRUE. The hardware reset is
disabled until bit 2 is reset to 0.
High-speed counter and pulse output
181