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7 MEMORY CONFIGURATION AND DATA PROCESS
7.2 Data transmission process
(1) Power supply ON/
Flash ROM
Parameter area (a)
Parameter area (b)
Positioning data area
(No.1 to 600)
Block start data area
(No.7000 to 7004)
The data is transmitted between the QD75 memories with steps (1) to (8) shown
below.
The data transmission patterns numbered (1) to (8) on the right page correspond to
the numbers (1) to (8) on the left page.
(4) FROM command
PLC CPU reset
ROM
PLC CPU
(2) TO command
Buffer memory
Parameter area (a)
Parameter area (b)
Positioning data area
(No.1 to 600)
Block start data area
(No.7000 to 7004)
Monitor data area
Control data area
PLC CPU
memo area
7 - 6
MELSEC-Q
QD75
Parameter area (a)
Pr.1 to
Pr.7
Pr.11
Pr.24
to
Pr.43
Pr.57
to
Pr.150
Parameter area (b)
Pr.8 to
Pr.10
Pr.25
Pr.42
to
(3) PLC READY signal
[Y0] OFF
ON
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Troubleshooting
