Fsb Source Synchronous 4X (Data) Timing Waveform - Intel BFCBASE - Motherboard - 7300 Datasheet

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Figure 2-18. FSB Source Synchronous 4X (Data) Timing Waveform
DSTBp# (@ driver)
DSTBn# (@ driver)
D# (@ driver)
DSTBp# (@ receiver)
DSTBn# (@ receiver)
D# (@ receiver)
50
T0
T
/4
T
/2
p
p
BCLK1
BCLK0
T
D
T
T
T
T
A
B
B
A
T
J
T
= T1: BCLK[1:0] Period
P
T
= T21: Source Sync. Data Output Valid Delay Before Data Strobe
A
T
= T22: Source Sync. Data Output Valid Delay After Data Strobe
B
T
= T28: Source Sync. Data Strobe Setup Time to BCLK
C
T
= T30: Data Strobe 'n' (DSTBN#) Output Valid Delay
D
T
= T25: Source Sync. Input Setup Time
E
T
= T26: Source Sync. Input Hold Time
G
T
= T20: Source Sync. Data Output Valid Delay
J
T1
3T
/4
p
T
T
T
T
E
G
E
G
Document Number: 318080-002
Electrical Specifications
T2
T
C

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