Voltage Identification Definition - Intel BFCBASE - Motherboard - 7300 Datasheet

Electrical Specifications
Table 2-3.

Voltage Identification Definition

VID6 VID5 VID4
HEX
400 200 100
mV mV mV
7A 1 1 1
78 1 1 1
76 1 1 1
74 1 1 1
72 1 1 1
70 1 1 1
6E 1 1 0
6C 1 1 0
6A 1 1 0
68 1 1 0
66 1 1 0
64 1 1 0
62 1 1 0
60 1 1 0
5E 1 0 1
5C 1 0 1
5A 1 0 1
58 1 0 1
56 1 0 1
54 1 0 1
52 1 0 1
50 1 0 1
4E 1 0 0
4C 1 0 0
4A 1 0 0
48 1 0 0
46 1 0 0
44 1 0 0
42 1 0 0
40 1 0 0
3E 0 1 1
Notes:
1. When this VID pattern is observed, the voltage regulator output should be disabled.
2. Shading denotes the expected VID range of the Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel®
Xeon® Processor 7300 Series.
3. The VID range includes VID transitions that may be initiated by thermal events, assertion of the FORCEPR# signal (see
Section 6.2.3), Extended HALT state transitions (see
(see Section 7.3). The Extended HALT state must be enabled for the processor to remain within its specifications.
4. Once the VRM/EVRD is operating after power-up, if either the Output Enable signal is de-asserted or a specific VID off code is
received, the VRM/EVRD must turn off its output (the output should go to high impedance) within 500 ms and latch off until
power is cycled. Refer to Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design
Guidelines.
Document Number: 318080-002
VID3 VID2 VID1
V
50 25 12.5
CC_MAX
mV mV mV
1 0 1 0.8500
1 0 0 0.8625
0 1 1 0.8750
0 1 0 0.8875
0 0 1 0.9000
0 0 0 0.9125
1 1 1 0.9250
1 1 0 0.9375
1 0 1 0.9500
1 0 0 0.9625
0 1 1 0.9750
0 1 0 0.9875
0 0 1 1.0000
0 0 0 1.0125
1 1 1 1.0250
1 1 0 1.0375
1 0 1 1.0500
1 0 0 1.0625
0 1 1 1.0750
0 1 0 1.0875
0 0 1 1.1000
0 0 0 1.1125
1 1 1 1.1250
1 1 0 1.1375
1 0 1 1.1500
1 0 0 1.1625
0 1 1 1.1750
0 1 0 1.1875
0 0 1 1.2000
0 0 0 1.2125
1 1 1 1.2250
Section
VID6 VID5 VID4
HEX
400 200 100
mV mV mV
3C 0 1 1
3A 0 1 1
38 0 1 1
36 0 1 1
34 0 1 1
32 0 1 1
30 0 1 1
2E 0 1 0
2C 0 1 0
2A 0 1 0
28 0 1 0
26 0 1 0
24 0 1 0
22 0 1 0
20 0 1 0
1E 0 0 1
1C 0 0 1
1A 0 0 1
18 0 0 1
16 0 0 1
14 0 0 1
12 0 0 1
10 0 0 1
0E 0 0 0
0C 0 0 0
0A 0 0 0
08 0 0 0
06 0 0 0
04 0 0 0
02 0 0 0
00 0 0 0
7.2.2), or Enhanced Intel SpeedStep
VID3 VID2 VID1
V
50 25 12.5
CC_MAX
mV mV mV
1 1 0 1.2375
1 0 1 1.2500
1 0 0 1.2625
0 1 1 1.2750
0 1 0 1.2875
0 0 1 1.3000
0 0 0 1.3125
1 1 1 1.3250
1 1 0 1.3375
1 0 1 1.3500
1 0 0 1.3625
0 1 1 1.3750
0 1 0 1.3875
0 0 1 1.4000
0 0 0 1.4125
1 1 1 1.4250
1 1 0 1.4375
1 0 1 1.4500
1 0 0 1.4625
0 1 1 1.4750
0 1 0 1.4875
0 0 1 1.5000
0 0 0 1.5125
1 1 1 1.5250
1 1 0 1.5375
1 0 1 1.5500
1 0 0 1.5625
0 1 1 1.5750
0 1 0 1.5875
0 0 1 1.6000
1
0 0 0 OFF
®
Technology transitions
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