Ferr#/Pbe# Valid Delay Timing; Vid Step Timings - Intel BFCBASE - Motherboard - 7300 Datasheet

Figure 2-25. FERR#/PBE# Valid Delay Timing
Notes:
1. Ta = T40 (FERR# Valid Delay from STPCLK# Deassertion).
2. FERR# / PBE# is undefined from STPCLK# assertion until the Stop-Grant acknowledge is driven on the
FSB. FERR# / PBE# is also undefined for a period of Ta from STPCLK# deassertion. Inside these undefined
regions, the PBE# signal is driven. FERR# is driven at all other times.
Figure 2-26. VID Step Timings
VID
V (max)
CC
V (min)
CC
54
BCLK
System bus
STPCLK#
FERR#/PBE# FERR# undefined
n
Tb
Ta = T84: VID Down to Valid V
Tb = T82: VID Down to Valid V
Tc = T85: VID Up to Valid V
Td = T83: VID Up to Valid V
SG
Ack
PBE#
...
n-1
Ta
(max)
CC
(min)
CC
(max)
CC
(min)
CC
Electrical Specifications
Ta
undefined FERR#
m m+1
Tc
Td
Document Number: 318080-002