Voltage Sequence Timing Requirements - Intel BFCBASE - Motherboard - 7300 Datasheet

Electrical Specifications
Figure 2-24. Voltage Sequence Timing Requirements
VID[6:1] / BSEL[2:0]
PWRGOOD
Reset Configuration
Signals(A[35:3]#,
INIT#, SMI#)
Reset Configuration
Signals BR[1:0]#
Document Number: 318080-002
Tc
V
TT
V
CCPLL
V
CC_BOOT
Vcc
Ta
BCLK
RESET#
Ta= T43 (V stable to VID[6:1] / BSEL[2:0] valid)
CC_BOOT
Tb= T44 (VID[6:1] / BSEL[2:0] valid to Vcc stable)
Tc= T48 (V stable to VID[6:1] / BSEL[2:0] valid)
TT
Td= T36 (PWRGOOD assertion to RESET# de-assertion)
Te= T41 (V stable to PWRGOOD assertion)
CC
Tf = T37 (BCLK stable to PWRGOOD assertion)
Tg = T49 (V stable to PWRGOOD assertion)
CCPLL
Th = T45 Reset Configuration Signals (A[35:3]#, BR[1:0]#, INIT#, SMI#) Setup Time
Ti= T46 Reset Configuration Signals (A[35:3]#, INIT#, SMI#) Hold Time
Tj= T47 Reset Configuration Signals (BR[1:0]#) Hold Time
Tg
Tb
Te
Tf Td
Th Ti
Tj
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