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Features
7
Features
7.1
Power-On Configuration Options
Several configuration options can be configured by hardware. The Intel
Processor 7200 Series and 7300 Series sample its hardware configuration at reset, on
the active-to-inactive transition of RESET#. For specifics on these options, please refer
to
Table
7-1.
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset. All resets reconfigure
the processor, for reset purposes, the processor does not distinguish between a "warm"
reset (PWRGOOD signal remains asserted) and a "power-on" reset.
Table 7-1.
Power-On Configuration Option pins
Execute BIST (Built-In Self Test)
Disable MCERR# observation
Disable BINIT# observation
Cluster ID / APIC ID[4:3]
Disable dynamic bus parking
Symmetric agent arbitration ID
Output tri state
Notes:
1.
Asserting this signal during RESET# will select the corresponding option.
2.
Address pins not identified in this table as configuration options should not be asserted during RESET#.
3.
Requires de-assertion of PWRGOOD.
Disabling of any of the cores within the Intel
Series must be handled by configuring the EXT_CONFIG Model Specific Register (MSR).
This MSR will allow for the disabling of a single core per die within the Intel
Processor 7200 Series and 7300 Series package..
7.2
Clock Control and Low Power States
The Intel
state (also referred to as C1E) in addition to the HALT state and Stop-Grant state to
reduce power consumption by stopping the clock to internal sections of the processor,
depending on each particular state. See
processor low power states. The Extended HALT state is a lower power state than the
HALT state or Stop Grant state.
The Extended HALT state must be enabled via the BIOS for the processor to
remain within its specifications. For processors that are already running at the
lowest bus to core frequency ratio for its nominal operating point, the processor will
transition to the HALT state instead of the Extended HALT state.
The Stop Grant state requires chipset and BIOS support on multiprocessor systems. In
a multiprocessor system, all the STPCLK# signals are bussed together, thus all
processors are affected in unison. When the STPCLK# signal is asserted, the processor
enters the Stop Grant state, issuing a Stop Grant Special Bus Cycle (SBC) for each
Document Number: 318080-002
Configuration Option
®
®
Xeon
Processor 7200 Series and 7300 Series supports the Extended HALT
Pin Name
A3#
A9#
A10#
A[12:11]#
A25#
BR[1:0]#
SMI#
®
®
Xeon
Processor 7200 Series and 7300
Figure 7-1
for a visual representation of the
®
®
Xeon
Notes
1,2
1,2
1,2
1,2
1,2
1,2
1,2,3
®
®
Xeon
111
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