Intel BFCBASE - Motherboard - 7300 Datasheet page 131

Features
7.4.3.4.5 MINV: Minimum Cache Voltage
This location contains the minimum Cache voltage. This field, rounded to the next
thousandth, is in mV and is reflected in hex. The minimum V
is the minimum allowable voltage assuming the FMB maximum current draw for two
processors. Writes to this register have no effect.
Example: The Intel
Cache VID. Offset 2D - 2Eh will contain 0000h (0 decimal).
Offset:
Bit
15:0
7.4.3.4.6 RES4: Reserved 4
These locations are reserved. Writes to this register have no effect.
Offset:
Bit
15:0
7.4.3.4.7 CDCKS: Cache Data Checksum
This location provides the checksum of the Cache Data Section. Writes to this register
have no effect.
Offset:
Bit
7:0
7.4.3.5 Package Data
This section provides package revision information.
7.4.3.5.1 PREV: Package Revision
This location tracks the highest level package revision. It is provided in ASCII format of
four characters (8 bits x 4 characters = 32 bits). The package is documented as 1.0,
2.0, etc. If this only consumes three ASCII characters, a leading space is provided in
the data field.
Example: The Intel
revision of the FC-mPGA6 package. Thus, at offset 32-35h, the data is a space followed
by 1.0. In hex, this would be 20h, 31h, 2Eh, 30h.
Document Number: 318080-002
® ®
Xeon Processor 7200 Series and 7300 Series does not utilize a
2Dh-2Eh
Minimum Cache Voltage
0000h-FFFFh: mV
2Fh-30h
RESERVED 4
0000h-FFFFh: Reserved
31h
Cache Data Checksum
One Byte Checksum of the Cache Data Section
00h- FFh: See Section 7.4.4 for calculation of the value
® ®
Xeon Processor 7200 Series and 7300 Series utilizes the first
Description
Description
Description
reflected in this field
CACHE
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